Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-17
2004-03-16
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000, C438S259000, C438S396000
Reexamination Certificate
active
06706589
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to the forming, in monolithic form, high-capacitance capacitors, for example for decoupling elements or resonant circuits, including metal armatures. More specifically, the present invention relates to the manufacturing of such capacitors by means of interconnection metallizations formed in the upper portion of an integrated circuit.
2. Discussion of the Related Art
FIGS. 1A
to
1
D illustrate, in a simplified partial cross-section view, a method for making such transistors. The method starts, as illustrated in
FIG. 1A
, with the deposition, on a substrate
1
, of an insulating layer
2
so that its upper surface is substantially planar. Substrate
1
is essentially formed of an insulating region, which may include vertical conductive contacts or vias. Layer
2
is then etched to form an opening
3
at the location where the capacitor is to be formed.
At the next steps, illustrated in
FIG. 1B
, a metal layer
4
corresponding to an interconnection metallization is deposited and a chem-mech polishing (CMP) is then performed to leave thereof the portion contained in opening
13
.
In the successive operation of filling of opening
3
and of leveling of layer
4
, a notch or depression
5
generally forms in the surface of metal layer
4
at the level of the contact area between layer
4
and insulating layer
2
. Notch
5
may have a depth on the order of a few tens of nanometers. Further, and although this has not been shown in the drawings, the leveling of material
4
is generally not perfect. It upper surface exhibits a dome rounded shape.
At the next step, illustrated in
FIG. 1C
, an insulating layer
6
of very small thickness, on the order of a few tens of nanometers, intended for forming the capacitor dielectric, is deposited and etched.
At the next steps, a second electrode is formed opposite to the first electrode.
According to an embodiment, illustrated in
FIG. 1D
, a second metal layer
7
is deposited and etched to be given the shape desired for the second electrode. A capacitor has thus been formed, two metal armatures
4
and
7
of which are separated by an insulator
6
.
A disadvantage of such a method is that the thickness of layer
6
cannot be as reduced as it would be desired. Indeed, its continuity must be ensured between the two electrodes. Now, notch
5
has a depth greater than the minimum thickness of layer
6
determined by the insulation criteria. If layer
6
is too thin, it risks exhibiting discontinuities in notch
5
.
To avoid this disadvantage, another conventional method for making a capacitor with two metal armatures provides initial steps similar to those previously described in relation with
FIGS. 1A
to
1
C. However, the second electrode is not directly etched, but rather formed by repeating the preceding steps. The result of such a method is illustrated in FIG.
2
.
After the deposition and etching of dielectric layer
6
previously described in relation with
FIG. 1C
, an insulating layer
8
is deposited and opened. Layer
8
is similar to layer
2
. Layer
8
is opened across a width W
3
. To guarantee that the fragile area including notches
5
is not covered, width W
3
is smaller than width W
1
of first electrode
4
. A metal layer
9
of a material similar to that of layer
4
is deposited and then leveled by CMP, as previously described in relation with FIG.
1
C.
A compared to the preceding method, this method has the advantage of avoiding that second electrode
9
covers the area including notch
5
. In terms of capacitance, this enables avoiding notch
5
and the associated leakage currents. However, this method has the disadvantage that the CMP leveling of layer
9
is relatively difficult. Indeed, as previously specified, the upper surface of layer
4
is not planar. This lack of surface evenness is reproduced by layer
9
, and this enhances the complexity of etching of the material of layer
9
. Further, the etching of insulating layer
8
by stopping on insulator
6
risks damaging it.
Further, whatever the method used, the capacitor surface area is equal to that of the smallest of the two portions of opposite interconnection layers and is limited by the available surface area above the integrated circuit.
Thus, as a non-limiting example, while the surface area available to create a capacitor ranges between 100 and 10
6
&mgr;m
2
, typically, 10000 &mgr;m
2
, the real capacitive coupling surface area ranges between 90 and 0.9.10
6
&mgr;m
2
, typically 9900 &mgr;m
2
. The capacitance of the obtained capacitors then ranges between 0.1 and 10
3
pF.
SUMMARY OF THE INVENTION
The present invention aims at providing a method for forming capacitors with metal armatures formed above an integrated circuit having for a same integration surface area a greater capacitance than that obtained by conventional methods by developing opposite surfaces.
Another object of the present invention is to provide such a method which avoids the previously-discussed manufacturing disadvantages.
To achieve these and other objects, the present invention provides a method for forming a capacitor with metal armatures in metallization levels above an integrated circuit, including the steps of:
a) depositing over the surface of an integrated circuit an insulating layer having a thickness ranging between 0.5 and 1.5 &mgr;m;
b) digging into the insulating layer to form trenches, of which at least a portion in top view is parallel and separate from one trench to the other;
c) depositing and leveling a metallic material to form conductive lines in the trenches;
d) locally removing the insulating layer to remove it at least from all the intervals separating two conductive lines;
e) conformally depositing a dielectric; and
f) depositing and etching a second metallic material to at least completely fill the intervals between lines.
According to an embodiment of the present invention, step a) of deposition of the insulating layer is preceded by the forming in the underlying integrated circuit of a metal plate, the next step b) of digging into the insulating layer being performed so that the trenches all expose at least partially said metal plate.
According to an embodiment of the present invention, step b) of digging into the insulating layer is performed to give to the trenches, in top view, a comb shape.
According to an embodiment of the present invention, the trenches are formed during step b) of digging into the insulating layer to have in top view the shape of two interdigited combs.
According to an embodiment of the present invention, step d) of removal of the insulating layer is performed across a given width ranging between 1 and 1.5 &mgr;m.
According to an embodiment of the present invention, the dielectric has a thickness ranging between 10 and 100 nm.
According to an embodiment of the present invention, step d) of local removal of the insulating layer is performed to draw a comb in top view.
According to an embodiment of the present invention, the second metallic material at step f) is deposited and etched to expose the planar portions of the dielectric covering the upper surfaces of the insulating layer and conductive lines of the first metallic material.
According to an embodiment of the present invention, the dielectric is silicon oxide or tantalum oxide.
According to an embodiment of the present invention, the first metallic material is copper, and the second metallic material is titanium or tungsten.
REFERENCES:
patent: 5162248 (1992-11-01), Dennison et al.
patent: 5270241 (1993-12-01), Dennison et al.
patent: 5480824 (1996-01-01), Jun
patent: 5804852 (1998-09-01), Yang et al.
patent: 5895250 (1999-04-01), Wu
patent: 5976981 (1999-11-01), Cheng
patent: 6207496 (2001-03-01), Kang
patent: 6300191 (2001-10-01), Yu et al.
patent: 6399440 (2002-06-01), Miao
patent: 6403444 (2002-06-01), Fukuzumi et al.
patent: 2001/0026987 (2001-10-01), Fazan et al.
patent: 0 862 203 (1998-09-01), None
French Search Report from French Patent Application 00 10697, filed
Arnal Vincent
Torres Joaquim
Jorgenson Lisa K.
Lebentritt Michael S.
Morris James M.
STMicroelectronics S.A.
Wolf Greenfield & Sacks P.C.
LandOfFree
Manufacturing of capacitors with metal armatures does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Manufacturing of capacitors with metal armatures, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing of capacitors with metal armatures will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3280544