Manufacturing method of semiconductor device with protection...

Details Manufacturing method of semiconductor device with protection... Manufacturing method of semiconductor device with protection...

2005-05-17

2005-05-17

Zarneke, David (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S301000

Reexamination Certificate

active

06893926

ABSTRACT:
A withstand voltage against electrostatic discharge of a high voltage MOS transistor is improved. An N−-type drain layer is not formed under an N+-type drain layer, while a P+-type buried layer is formed in a region under the N+-type drain layer. A PN junction of high impurity concentration is formed between the N+-type drain layer and the P+-type buried layer. In other words, a region having low junction breakdown voltage is formed locally. The surge current flows through the PN junction into the silicon substrate before the N−-type drain layer below a gate electrode is thermally damaged. Hence, the ESD withstand voltage is improved.

REFERENCES:
patent: 5397905 (1995-03-01), Otsuki et al.
patent: 6489653 (2002-12-01), Watanabe et al.
patent: 6638827 (2003-10-01), Kikuchi et al.

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