Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-11-27
2004-11-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06815284
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a manufacturing method of a semiconductor device, specifically to an ion-implantation technology to control a threshold voltage of a high voltage MOS (Metal Oxide Semiconductor) transistor used for various drivers such as an LCD driver, especially a gate driver using a TFT (Thin Film Transistor).
2. Description of the Related Art
Manufacturing method of a semiconductor device according to a conventional art will be explained hereinafter referring to
FIGS. 12 and 13
.
FIG. 12
is a cross-sectional view of a high voltage P channel open drain MOS transistor.
As shown in
FIG. 12
, an N-type well region (NW)
52
is formed in a P type semiconductor substrate (P-sub)
51
, on which a first gate insulation film
53
A and a second gate insulation film
53
B, each having a different thickness from each other, are formed. A selective oxidation film
53
C is formed in the same process step as an element isolation film
53
D. A gate electrode
54
is formed over the first and the second gate insulation films
53
A and
53
B and the selective oxidation film
53
C.
A P+ type source region
55
is formed adjacent one end of the gate electrode
54
and a P− type drain region
57
is formed facing the source region
55
with a channel region
56
between them. Also, a P+ type drain region
58
is formed away from the other end of the gate electrode
54
and surrounded by the P− type drain region
57
.
Then, an interlayer insulation film
59
is formed on the entire surface followed by a formation of a metal interconnect
60
which contacts with the source and the drain regions
55
and
58
, respectively, through contact holes formed in the interlayer insulation film
59
.
As described above, the high voltage MOS transistor has the first gate insulation film
53
A and the second gate insulation film
53
B, each having the different thickness from each other.
There has been a problem as described below in an ion-implantation process to adjust a threshold voltage of the high voltage MOS transistor of such a structure.
When implanting ions under the first and the second gate insulation films
53
A and
53
B to adjust the threshold voltage, the ion-implantation for the threshold voltage adjustment is performed after a conductive film
54
A for forming the gate electrode is formed on the gate insulation films
53
A and
53
B, as shown in FIG.
13
.
When the ions for the threshold voltage adjustment are implanted in a single ion-implantation process step under both of the first and the second gate insulation films
53
A and
53
B, each having the different thickness from each other, an impurity concentration profile in a region A (under the thin gate insulation film) becomes different from that in a region B (under the thick gate insulation film). The ions for the threshold voltage adjustment are not implanted into a region C under the selective oxidation film
53
C.
That is, an ion-implanted layer
61
A in the region A under the thin gate insulation film is deeper than an ion-implanted layer
61
B in the region B under the thick gate insulation film, as shown in FIG.
13
. In this case, there arises a problem that the threshold voltage in the region A is reduced compared to that in the region B, since the impurity concentration is higher and the gate insulation film is thinner in the region A than in the region B.
Therefore, it has been necessary to perform ion-implantation process steps for the threshold voltage adjustment to the region A and to the region B separately, in order to adjust the threshold voltages in the region A and in the region B. Accordingly, two photoresist masks are required in the manufacturing method of the conventional art, resulting in two individual processing steps to achieve a desirable threshold voltage in the regions A, B.
SUMMARY OF THE INVENTION
Considering the problems addressed above, a manufacturing method of this invention has process steps for threshold voltage adjustment, to provide a semiconductor substrate of one conductivity type, to form a first well of an opposite conductivity type in the substrate, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each film having different thickness from each other, to ion-implant first impurities of the one conductivity type into both of the wells under conditions that the first impurity ions penetrate both of the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well under conditions that the second impurity ions penetrate the thin gate insulation film but do not penetrate the thick gate insulation film.
The second well of the opposite conductivity type is formed to offset the first impurities of the one conductivity type.
The thin gate insulation film is formed after the process step to form the thick gate insulation film.
Or the thin gate insulation film is formed before the process step to form the thick gate insulation film.
Furthermore, the manufacturing method of the semiconductor device of this invention includes a process step to form a selective insulation film by selective oxidation of the semiconductor substrate with a mask of an oxidation resistant film formed on the predetermined region of the semiconductor substrate, a process step to form the thick gate insulation film bordering on the selective insulation film after removing the oxidation resistant film, a process step to form the thin gate insulation film bordering on the thick gate insulation film by thermal oxidation of the substrate after removing a portion of the thick gate insulation film, a process step to form a gate electrode across the thin gate insulation film, thick gate insulation film and the selective insulation film and a process step to form a source region bordering the gate electrode through the thin gate insulation film and a drain region bordering the gate electrode through the selective insulation film.
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Kikuchi Shuichi
Momen Masaaki
Uehara Masafumi
Fourson George
Kebede Brook
Sanyo Electric Co,. Ltd.
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