Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-26
2004-07-27
Gurley, Lynne (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S402000, C438S476000, C438S906000, C257S632000
Reexamination Certificate
active
06767782
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing technique of a semiconductor device, and particularly to a technique to be effectively applied to a manufacturing method of a semiconductor device, which has a manufacturing process using plasma.
A thin gate insulating film is indispensable for a MISFET (Metal Insulator Semiconductor Field Effect Transistor). When the thickness of a gate insulating film decreases, the gate capacity per unit area increases and the coupling between a gate electrode and the surface of a substrate is improved and thereby a charge density and a drain current of an inversion layer are increased. That is, by decreasing the thickness of the gate insulating film, it is possible to improve the mutual conductance of the MISFET.
However, when the thickness of the gate insulating film is decreased to 10 nm or less, a breakdown phenomenon of the gate insulating film occurs and thereby the reliability of a semiconductor device is deteriorated. As a result of study by the present inventors, it has been clarified that particularly, the dielectric breakdown of a gate insulating film generated in a manufacturing process employing plasma used in a plasma CVD (Chemical Vapor Deposition) method or a plasma etching method or the like causes a serious problem.
Charge-up on a substrate due to electrons or positive ions generated by plasma is considered as one of the causes of the dielectric breakdown. That is, it has been estimated that the gate insulating film is broken because electric charges generated on a substrate due to a plasma reaction flow to a substrate and moreover to the ground potential through a susceptor of a manufacturing system on which the substrate is located. Therefore, to prevent occurrence of the above charge-up on the substrate, it is important to reduce electric charges flowing between the substrate and the susceptor of the manufacturing system by forming an insulating film therebetween.
Japanese Patent Laid-Open No. 7-106306 by Sasaki et al. discloses a method of using, in an ion etching system, a structure of attaching a polyimide film to the surface of a bottom electrode and of setting the wafer on the polyimide film and thereby dispersing a voltage applied to a wafer to the polyimide film, a blocking capacitor and the wafer.
Moreover, Japanese Patent Laid-Open No. 8-111409 by Nakajima et al. discloses a method of forming an oxide film made of a semiconductor wafer material on the back of a semiconductor wafer at least before a step of first forming a film on the surface of the semiconductor wafer through a CVD method, and leaving the oxide film on the back of the semiconductor wafer at least after a final film-forming step through a CVD method, and thereby suppressing the warpage of the semiconductor wafer.
Furthermore, Japanese Patent Laid-Open No. 9-45680 by Ogawa discloses a method for reducing the warping amount of a silicon-substrate wafer by forming a refractory metallic thin film on the surface of a semiconductor substrate and then depositing an insulating film having a tensile stress on the whole back of the semiconductor substrate.
Furthermore, Japanese Patent Laid-Open No. 2000-91175 by Matsumoto et al. discloses a method for preventing copper or the like produced due to a heat treatment from diffusing into a wafer by forming a protective film made of a material having a small copper (Cu) diffusion coefficient on the circumferential portion, outer peripheral surface, and back of the main surface of a wafer.
Furthermore, Japanese Patent Laid-Open No. 2000-150640 by Aoki discloses a method for forming a barrier film made of a silicon oxide film or the like on the back of the semiconductor substrate, and then forming a copper-based metallic film on the main surface of the semiconductor substrate, and thereby preventing characteristics of a device from deteriorating and a current therein from leaking due to metallic contaminant adhering to the back of a semiconductor substrate.
SUMMARY OF THE INVENTION
In the case of a manufacturing device using plasma, a wafer is mounted on a susceptor in a reaction chamber and fabricated through plasma CVD or plasma etching or the like. In general, the surface of a susceptor of a manufacturing system is covered with an insulating film having a thickness of about rf 10 &mgr;m and a wafer is insulated from the susceptor. However, as a result of study by the present inventor, it is clarified that an insulating film on a susceptor is deteriorated as the frequency of using the insulating film increases, a pinhole is locally formed, and a current path from a wafer to the susceptor is formed.
Moreover, a manufacturing device using plasma and adopting an electrostatic attraction system frequently uses conductive ceramic having a conductivity of tens to hundreds M&OHgr;cm for a susceptor in order to increase the attraction force of a wafer and make the wafer more easily separate from the susceptor. In this case, because electric charges easily flow between the wafer and the susceptor, it is impossible to avoid a problem of damages caused by charge-up.
Furthermore, various studies have been made of an insulating film formed between a wafer and the susceptor of a manufacturing system of, for example, an insulating film formed on the back of the wafer. However, the study for reducing charge-up generated on a substrate due to a plasma reaction including a manufacturing process of a semiconductor device has not been sufficiently made of so far. Therefore, reduction in charge-up due to plasma has been left as an important problem on a high integrated semiconductor device.
An object of the present invention is to provide a technique capable of reducing charge-up damages on a substrate in a manufacturing process using plasma and a technique capable of improving the reliability of a semiconductor device.
The above and other objects and novel features of the present invention will become more apparent from the description of this specification and the accompanying drawings.
The outline of a typical invention among inventions disclosed in this application will be briefly described below.
The present invention forms both a gate insulating film of a MISFET formed on a first main surface of a substrate and a first insulating film covering a gate electrode, then forms a second insulating film on a second main surface of a substrate, or a bevel portion of the substrate, or both the second main surface and the bevel portion of the substrate, and then forms a wiring layer on the first main surface of the substrate. It is preferable that the above-mentioned second insulating film is constituted by a TEOS oxide film, silicon nitride film, or silicon oxide film formed through CVD plasma and its thickness is about 100 nm or more.
Moreover, outlines of other inventions of this application will be briefly described below by classing them into items.
1. A manufacturing method of a semiconductor device, comprises (a) a step of forming a first insulating film on a first main surface of a substrate, (b) a step of forming a second insulating film on a second main surface of the substrate, and (c) a step of polishing the first insulating film through a CMP method, wherein a wiring layer is formed on the first main surface of the substrate after the step (c) is executed.
2. A manufacturing method of a semiconductor device, comprises (a) a step of forming a first insulating film on a first main surface of a substrate and then forming a connection hole in a predetermined area of the first insulating film, (b) a step of forming a metallic film on the first main surface of the substrate, (c) a step of forming a second insulating film on a second main surface of the substrate, and (d) a step of polishing the metallic film through a CMP method and forming a plug in the connection hole, wherein a wiring layer is formed on the first main surface of the substrate after the step (d) is executed.
3. The manufacturing method of a semiconductor device according to item 1 or 2, wherein the second insulating film covers a bev
Maeno Ryohei
Ohmori Kazutoshi
Okudaira Sadayuki
Saikawa Takeshi
Saito Tetsuo
Gurley Lynne
Miles & Stockbridge P.C.
Renesas Technology Corp.
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