Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2011-06-14
2011-06-14
Doan, Theresa T (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S396000, C257S303000, C257S306000
Reexamination Certificate
active
07960227
ABSTRACT:
After a first via hole leading to a ferroelectric capacitor structure are formed in an interlayer insulating film by dry etching, a second via hole to expose part of the ferroelectric capacitor structure is formed in a hydrogen diffusion preventing film so as to be aligned with the first via hole by wet etching, and a via hole constructed by the first via hole and the second via hole communicating with each other is formed.
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Japanese Office Action, Partial English-language translation, mailed Nov. 9, 2010 for corresponding Japanese Application No. 2006-089312.
USPTO, [DOAN] “U.S. Appl. No. 11/495,769 (parent)”,[CTRS] Requirement for Restriction/Election issued on Feb. 25, 2008.
USPTO, [DOAN] “U.S. Appl. No. 11/495,769 (parent)”,[CTNF] Non-Final Rejection issued on Aug. 6, 2008.
USPTO, [DOAN] “U.S. Appl. 11/495,769 (parent)”,[CTFR] Final Rejection issued on Mar. 18, 2009.
Hayashi Yasuhiro
Izumi Kazutoshi
Doan Theresa T
Fujitsu Patent Center
Fujitsu Semiconductor Limited
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