Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-10-24
2009-08-04
Picardat, Kevin M (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S301000
Reexamination Certificate
active
07569455
ABSTRACT:
A manufacturing method of a CMOS semiconductor device includes using, in an nMOS, spike RTA (first annealing) together with ultra-rapid rising/falling temperature annealing (second annealing) whose temperature increase/decrease rate is higher than that of the spike RTA, and applying the ultra-rapid rising/falling temperature annealing (second annealing) alone in a pMOS, when activating a shallow source/drain extension region.
REFERENCES:
patent: 6551870 (2003-04-01), Ling et al.
patent: 6632718 (2003-10-01), Grider et al.
patent: 7157340 (2007-01-01), Ito et al.
patent: 2001/0041432 (2001-11-01), Lee
patent: 2005/0263835 (2005-12-01), Sakama et al.
patent: 2006/0073665 (2006-04-01), Jain
patent: 2006/0199346 (2006-09-01), Jain
patent: 2004-63574 (2004-02-01), None
patent: 2005-5406 (2005-01-01), None
patent: 2006-278532 (2006-10-01), None
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Picardat Kevin M
LandOfFree
Manufacturing method of semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Manufacturing method of semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method of semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4090824