Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-10-30
2002-05-14
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S261000, C438S593000
Reexamination Certificate
active
06387756
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a non-volatile semiconductor device.
2. Description of the Related Art
Taking the case of a flash memory as an example, a conventional manufacturing method of a non-volatile semiconductor device is described below.
First, as shown in FIG.
4
(
a
), element isolation regions
2
are formed on a silicon substrate
1
by an ordinary method, and a silicon oxide film is formed on the surface of the silicon substrate. Through this silicon oxide film, ion implantation of dopants such as boron is, then, applied over the surface of the silicon substrate so as to set a prescribed threshold value. Next, after this silicon oxide film is removed, a tunnel oxide film
3
made of a silicon oxide film is formed by the thermal oxidation method.
Next, as shown in FIG.
4
(
b
), a polysilicon layer
4
which is to serve later as a floating gate is grown over the entire surface. The dopants to provide the conductivity can be introduced thereinto, together with forming the polysilicon layer or afterwards through ion implantation. In this instance, concurrently with formation of the polysilicon layer, N-type dopants such as P are introduced thereinto.
Next, as shown in FIG.
4
(
c
), the polysilicon layer
4
is patterned by means of lithography and dry etching to form a floating gate
5
.
After that, as shown in FIG.
4
(
d
), an inter-gate insulating film
6
of an ONO film (a silicon oxide film/a silicon nitride film/a silicon oxide film) or the like is formed.
Next, after a polysilicon layer is formed over the entire surface, ion implantation of N-type dopants such as P and, then, patterning by means of lithography and dry etching are applied thereto, which forms a control gate
7
, as shown in FIG.
4
(
e
).
Subsequently, for source-drain formation, ion implantation of dopants is carried out by an ordinary method.
The manufacturing method of a non-volatile semiconductor device as described above has, however, the following problem.
That is, as shown in afore-mentioned FIG.
4
(
c
), a floating gate formed by a conventional method has, at each end, a ridge section rising steeply to form an acute vertical angle, and besides the gate surface thereof is uneven due to the presence of polysilicon grains. Consequently, in the structure (FIG.
4
(
e
)) wherein an inter-gate insulating film
6
and a control gate
7
are formed over a floating gate of this sort, electric field centralization may occur locally in the ridge sections at both ends of the floating gate and in uneven places on the surface of the floating gate and give rise to the leakage current. This causes dispersion and deterioration of element characteristics of semiconductor device such as dispersion of the erasure and deterioration of hold characteristics. The generation of such leakage current is considerable, especially in the ridge sections at both ends of the floating gates in the semiconductor device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a manufacturing method of a non-volatile semiconductor device that can overcome the above problem and produce a non-volatile semiconductor device having excellent hold characteristics and only a small dispersion of element characteristics.
The present invention relates to a method of manufacturing a non-volatile semiconductor device having a structure in which layers of a first insulating film, a first polysilicon layer, a second insulating film and a second polysilicon layer are formed, in this order, on a semiconductor substrate; which comprises the steps of:
forming the first insulating film on the semiconductor substrate and thereafter forming the first polysilicon layer;
patterning the first polysilicon layer;
performing a heat treatment in hydrogen atmosphere;
forming the second insulating film;
forming the second polysilicon layer; and
patterning the second polysilicon layer.
The present invention can suppress the dispersion and the deterioration of element characteristics that is the very problem of the conventional manufacturing methods. Furthermore, because the inter-gate insulating film can be made considerably thin, the erasing voltage can be reduced, allowing the semiconductor device to operate at lower voltages.
REFERENCES:
patent: 6187632 (2001-02-01), Shuto et al.
patent: 08-330198 (1996-12-01), None
patent: 10-284588 (1998-10-01), None
Bowers Charles
Chen Jack
McGinn & Gibb PLLC
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