Manufacturing method of MOSFET having salicide structure

Details Manufacturing method of MOSFET having salicide structure Manufacturing method of MOSFET having salicide structure

1998-09-09

2001-03-06

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S303000, C438S595000

Reexamination Certificate

active

06197648

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a manufacturing method of semiconductor device, and more particularly to a MOSFET of so-called salicide structure having a silicide layer on a source region, on a drain region, and on a gate electrode.
FIG. 1
shows a plane pattern of a conventional semiconductor device.
A semiconductor substrate
11
is divided into an element isolation region
12
, and an element region
13
. In the element isolation region
12
, a field oxide film by LOCOS method, or a silicon oxide film in STI (Shallow Trench Isolation) structure is formed. In the element region
13
, a MOSFET is formed. The MOSFET is composed of a gate electrode
14
, and source and drain regions
15
formed in the semiconductor substrate
11
at both sides of the gate electrode
14
.
In such semiconductor device, the interval of gate electrodes
14
of two MOSFETs adjacent to each other is expressed by W. Hitherto, by minimizing this interval W, it has been attempted to reduce the area of one MOSFET occupying on the semiconductor substrate
11
, and mount the MOSFETs on the semiconductor substrate
11
at high density.
FIG. 2
shows a conventional semiconductor device attempted to enhance the density of MOSFETs.
FIG. 3
shows a sectional view along line III—III in FIG.
2
.
It is a first feature of this semiconductor device that the contact of the source and drain regions
15
of the MOSFET is achieved at one position only at the end of the source and drain regions
15
so as to minimize the interval W of the gate electrodes
14
of two MOSFETs adjacent to each other.
In this case, it contributes to enhancement of density of MOSFETs, but the length Y of the source and drain regions
15
is extremely short, and its resistance value is large. As a result, the potential in the contact area
16
and the potential at a position remote from the contact area
16
are different, and the characteristic of the MOSFET is impaired.
Hence, it is a second feature herein that a silicide layer
17
is formed on the source and drain regions
15
. The silicide layer
17
is low in the resistance value, and is effective for suppressing the potential drop between the contact area
16
and a position remote from the contact area
16
. In this example, the salicide structure is employed by forming a silicide layer
17
also on the gate electrode
14
aside from the source and drain regions
15
.
On the other hand, as the MOSFET becomes smaller in size, the LDD structure is often employed for alleviating the electric field near the source and drain regions at the end of the gate electrode
14
. The LDD structure is composed of a low density doping region
18
having a lower concentration than the concentration of the source and drain regions
15
.
Incidentally, when the length X of the gate electrode
14
is about 0.25 microns (250 nm), the length Y of the source and drain regions
15
is set at about 200 nm. To realize the LDD structure, the width a of a side wall insulating film (spacer)
19
must be least 100 nm in consideration of the extended width (about 50 nm) h of the source and drain regions
15
due to thermal diffusion.
That is, the width b of possible silicide forming region is Y-a (about 100 nm). Usually, the width Z of the source and drain regions is several microns, and if the resistance value R of the silicide layer
17
is low, as shown in
FIG. 4
, a potential drop occurs between the contact area
16
and a position remote from the contact area
16
due to this resistance value R, and the characteristic of the MOSFET is impaired.
To prevent such potential drop, the width a of the side wall insulating film
19
must be reduced, but if the width a of the side wall insulating film
19
is too narrow, the source and drain regions
15
may cover the low density doping region
18
by the lateral diffusion of the source and drain regions
15
, thereby worsening the short channel effect of the MOSFET.
Thus, conventionally, the potential drop in the source and drain regions was prevented by forming a silicide layer on the source and drain region, but in the case of MOSFET having LDD structure, when the length of the source and drain regions becomes short, the region for forming the silicide layer is decreased by the portion of the thickness (width) of the side wall insulating film for LDD, and the potential drop cannot be prevented sufficiently.
BRIEF SUMMARY OF THE INVENTION
The invention is devised to solve the above problems, and it is hence an object thereof to present a manufacturing method of semiconductor device capable of sufficiently preventing potential drop in the source and drain regions by the silicide layer on the source and drain regions even in the MOSFET having LDD structure.
To achieve the object, the manufacturing method of semiconductor device of the invention comprises the steps of forming a gate electrode on a semiconductor substrate, forming a low density doping region by ion implantation of impurities in the semiconductor substrate by using the gate electrode as the mask, forming a first insulating film for covering the gate electrode on the semiconductor substrate, forming a second insulating film having an etching selective ratio to the first insulating film on the first insulating film, forming a side wall insulating film composed of a laminate film of the first and second insulating films only on the side wall of the gate electrode by etching the first and second insulating films by anisotropic etching, forming source and drain regions by ion implantation of impurities into the semiconductor substrate by using the gate electrode and the side wall insulating film as the mask, removing the second insulating film, and forming a silicide layer on the source and drain regions after narrowing the width of the side wall insulating film by etching the first insulating film by anisotropic etching.
The width of the side wall insulating film is equal to the thickness of the first and second insulating films at the time of ion implantation for forming the source and drain regions, and is equal to the thickness of the first insulating film at the time of forming the silicide layer on the source and drain regions.
The so-called salicide structure may be formed by forming a silicide layer on the gate electrode simultaneously when forming the silicide layer on the source and drain regions.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 5770508 (1998-06-01), Yeh et al.
patent: 5783475 (1998-07-01), Ramaswami
patent: 5817563 (1998-06-01), Lim
patent: 7-263682 (1995-10-01), None

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