Manufacturing method of flash memory device

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S211000, C257S314000, C257S900000, C257SE21422, C257SE21640, C257SE29129

Reexamination Certificate

active

07871885

ABSTRACT:
Embodiments relate to a manufacturing method of a flash memory device which improves electrical characteristics by reducing or preventing void generation. A manufacturing method of a flash memory device according to embodiments includes forming a plurality of gate patterns over a semiconductor substrate including a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate. A spacer layer may be formed as a compound insulating layer structure over the side wall of the gate pattern. A source/drain area may be formed over the semiconductor substrate at both sides of the control gate. An insulating layer located at the outermost of the spacer layer may be removed. A contact hole may be formed between the gate patterns by forming and patterning the interlayer insulating layer. A contact plug may be formed in the contact hole.

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patent: 2002/0192915 (2002-12-01), Wada et al.
patent: 2003/0216004 (2003-11-01), Jeong et al.
patent: 2005/0048754 (2005-03-01), Yeh et al.
patent: 2006/0163678 (2006-07-01), Anezaki
patent: 1591823 (2005-03-01), None
patent: 2000174270 (2000-06-01), None

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