Manufacturing method of DRAM Cell formed on an insulating layer

Details Manufacturing method of DRAM Cell formed on an insulating layer Manufacturing method of DRAM Cell formed on an insulating layer

1997-10-21

1999-03-30

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, 438268, H01L 218242

Patent

active

058888640

ABSTRACT:
A semiconductor memory device has a plurality of memory cells arranged in a matrix array, wherein each memory cell has a transistor and a capacitor and the transistor includes a vertical channel. The each memory cell includes a first junction region surrounded by the field oxide layer; a vertical channel including side surfaces, an upper portion and a lower portion, the lower portion of the vertical channel coupled to the first junction region; a second junction region coupled to the upper potion of the vertical channel; a gate electrode surrounding the side surfaces of the vertical channel and including a gate insulator located between the gate electrode and the side surfaces of the vertical channel; a charge storage electrode containing side surfaces, an upper portion and lower portion, the upper potion of the charge storage electrode coupled to the first junction region; a dielectric layer formed on the lower porion and the side surfaces of the charge storage electrode; and a plate electrode entirely surrounding the dielectric layer.

REFERENCES:
patent: 5001526 (1991-03-01), Gotou
patent: 5547889 (1996-08-01), Kim
patent: 5780335 (1998-07-01), Henkels et al.
patent: 5804478 (1998-09-01), Nagata et al.

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