Manufacturing method of CMOS devices

Details Manufacturing method of CMOS devices Manufacturing method of CMOS devices

2001-07-19

2004-11-09

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S369000

Reexamination Certificate

active

06815279

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-042729, filed Feb. 22, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor device using a tensile-strained Si layer and a compressive-strained Si—Ge layer as the channel layers infield-effect transistors and a method of manufacturing the semiconductor device.
In ordinary semiconductor devices, a Si bulk has been used as a substrate and high-speed operation and less power consumption have been achieved by miniaturizing the constituting elements of the semiconductor devices. The miniaturization, however, is now coming closer to the physical and economical limitations. Thus, in the future, it will be necessary to establish the techniques for achieving high-speed operation and less power consumption by other approaches than the miniaturization.
For instance, the technique for achieving high-speed operation by using metal gates for gate electrodes to suppress delay in the wiring of gates has been developed. To form metal gates and high dielectric gate insulating films in CMOSFETs, a dummy gate process has been proposed (A. Chatterjee, et al., IEDM Tech. Dig., 1997, p. 821 and A. Chatterjee, et al., Japanese Patent Laid Open (kokai) No. 7-321222). The dummy gate process includes a process of forming a dummy gate, which is disposed in advance, in a region in which an actual gate is to be formed, then forming a source and a drain by self-alignment techniques with the dummy gate as a mask, and thereafter replacing the dummy gate with the actual gate.
The technique has difficulty of adjusting the threshold voltage of the transistor due to the influence of the work function of the metal gate. For instance, when a gate electrode is made of TiN, the value of the work function ranges from 4.3 to 4.6 eV. Thus, the gate electrode has the problem that the threshold voltage is higher than that of a conventional polysilicon electrode by about 0.4 to 0.5V.
To improve the carrier mobility in a channel layer, the technique for using a tensile-strained Si layer on an Si—Ge layer (under a tensile stress) as the channel layer of an N-MOS transistor and a compressive-strained Si—Ge layer (under a compressive stress) as the channel layer of a P-MOS transistor has been reported (K. Ismail, “Si/Si—Ge High-Speed Field-Effect Transistors,” IEDM Tech. Dig., 1995, p.509). By using a tensile-strained Si layer or a compressive-strained Si—Ge layer as the channel layers of MOS transistors, the mobility of electrons and holes at the surface increases, making high-speed operation compatible with less power consumption.
This technique, however, has the following problem: when a CMOSFET with a tensile-strained Si layer (n-channel layer) and a compressive-strained Si—Ge layer (p-channel layer) both formed as the channel layers is formed, the processes are complex and it is difficult to selectively form an NMOS channel layer and a PMOS channel layer. Since an Si—Ge layer is formed by a high-temperature heat treatment, the Si—Ge layer misfit dislocation or the segregation of Ge takes place, thereby degrading the gate breakdown voltage characteristic.
It is known that, when a MOSFET is operated on an SOI substrate, holes are accumulated in the substrate at the end of the channel layer (near the source) and what is called the floating body effect occurs, having an adverse effect on the operation of the device. To suppress the floating body effect, a method of making the source region of Si—Ge material to make the bandgap smaller than that of the channel layer (Si) and thereby drawing holes into the source region has been proposed (Akira Nishiyama, et al., “Formation of Si—Ge source/drain using Ge implantation for floating-body effect resistant SOI MOSFETs,” Jpn. J. Appl. Phys. Vol. 35, pp. 954-959, Part 1, No. 28, February 1996).
This method, however, has the problem of being unable to make the channel layer of Si—Ge material. That is, the method cannot make the improvement of the mobility of holes compatible with the suppression of the floating body effect.
As described above, an FET using a metal gate cannot secure sufficient driving current because of its higher threshold voltage.
Furthermore, it is difficult to form a CMOSFET in which an NMOSFET using a tensile-strained Si layer formed on an Si—Ge layer as a channel layer and a PMOSFET using a compressive-strained Si—Ge layer as a channel layer are used.
In addition, when the source region is made of Si—Ge material to make the bandgap smaller than that of the channel layer and thereby suppress the floating body effect of the FET formed at the surface of an SOI substrate, the Si—Ge material cannot be used for the channel layer, which prevents the device from operating faster.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of lowering the threshold voltage of a CMOSFET using a metal gate and improving the driving capability or the speed of the device and a method of manufacturing the semiconductor device.
Another object of the present invention is to provide a semiconductor device manufacturing method of easily forming a CMOSFET in which an NMOSFET using a tensile-strained Si. layer as a channel layer and a PMOSFET using a Si—Ge layer as a channel layer are used.
Still another object of the present invention is to provide a semiconductor device capable of making the improvement of the mobility of electrons in an FET formed at the surface of an SOI substrate compatible with the suppression of the floating body effect.
In a semiconductor device according to the present invention in which an NMOSFET and a PMOSFET have been formed in a silicon substrate, the gate electrodes of the NMOSFET and PMOSFET are made of metallic materials, an Si—Ge layer is formed in at least part of the surface regions including the respective channel layers of the NMOSFET and PMOSFET, and the concentration of Ge in the channel layer of the NMOSFET is lower than the concentration of Ge in the channel layer of the PMOSFET.
Preferred modes of the semiconductor device according to the present invention are as follows:
(a) The silicon substrate is an SOI substrate and the concentration of Ge in the channel layer of the MOSFET is lower than the concentration of Ge in the source of the MOSFET.,
(b) An Si layer on the Si—Ge layer is used as the channel layer of the NMOSFET and the Si—Ge layer is used as the channel layer of the PMOSFET. The thickness of the Si layer on the Si—Ge layer is ranged between 2 nm to 30 nm. The Si—Ge layer of the NMOSFET is formed as Si
1−x
Ge
x
(0.1≦×≦0.9).
(c) A stacked structure of the Si—Ge layer and Si layer is formed only almost under the gate electrode of the channel region of the NMOSFET.
(d) The height of the surface of the gate electrode of the NMOSFET is equal to the height of the surface of the gate electrode of the PMOSFET.
(e) Gate insulating films for the NMOSFET and PMOSFET are made of Ta
2
O
5
.
(f) The part of the respective gate electrodes of the NMOSFET and PMOSFET are made of TiN.
(g) Gate insulating films for the NMOSFET and PMOSFET are made of Ta
2
O
5
and the part of the respective gate electrodes of the NMOSFET and PMOSFET are made of TiN.
In a semiconductor device according to the present invention in which an NMOSFET is formed on a silicon substrate, the gate electrode of the NMOSFET is made of metallic material, and a tensile-strained Si layer on an Si—Ge layer is used as the channel layer of the NMOSFET.
Preferred modes of the semiconductor device are as follows:
(a) The silicon substrate is an SOI substrate and the concentration of Ge in the channel layer of the MOSFET is lower than the concentration of Ge in the source of the MOSFET.
(b) An Si layer on the Si—Ge layer is used as the channel layer of the NMOSFET and the Si—Ge layer is used as the channel layer of the PMOSFET.
(c) A stacked structure of the Si—Ge layer and S

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