Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-03
2001-12-18
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S241000, C438S396000, C438S398000
Reexamination Certificate
active
06331462
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device and, more particularly, to a manufacturing method of a semiconductor device suitable for manufacturing a semiconductor device that comprises both a DRAM (dynamic random access memory) and peripheral circuits such as logic circuits.
2. Description of the Background Art
FIG. 12
is a cross-sectional view showing a conventional structure of a semiconductor device that comprises both a DRAM and peripheral circuits such as logic circuits on a single substrate (called the DRAM hybrid IC hereunder). In that conventional DRAM hybrid IC, an isolation oxide film
2
is furnished on a semiconductor substrate
1
. On the semiconductor substrate
1
are gate electrodes
6
made of a polysilicon layer
3
, a tungsten (W) layer
4
and an oxide film
5
stacked one upon another.
The polysilicon layer
3
is made either of implanted polysilicon formed by implanting impurities into an impurity-free silicon layer, or of doped polysilicon deposited in a manner mixed with impurities. The polysilicon layer
3
and tungsten layer
4
constitute a conductive layer of a tungsten silicide structure.
The silicon substrate
1
of the DRAM hybrid IC carries on it components of a DRAM and those of peripheral circuits. In the description that follows, the area in which the DRAM components are provided is called the DRAM area, and the area where the peripheral circuit components are furnished is called the peripheral circuit area. In the conventional DRAM hybrid IC, the silicon substrate
1
has gate electrodes
6
of the same structure formed in both the DRAM area and the peripheral circuit area.
Each gate electrode
6
is surrounded by a silicon nitride film
7
. In the DRAM area, the silicon nitride film
7
is formed so as to cover the top and sides of each gate electrode
6
; in the peripheral circuit area, the silicon nitride film
7
is formed to constitute side walls of the gate electrodes
6
.
The semiconductor substrate
1
further carries on it bit lines
10
of a tungsten silicide structure formed by a polysilicon layer
8
and a tungsten layer
9
. As with the polysilicon layer
3
mentioned above, the polysilicon layer
8
is made of either implanted polysilicon or doped polysilicon. The bit lines
10
are formed inside contact holes that are manufactured by known self-alignment techniques.
Interlayer insulating films
11
and
12
are formed over the semiconductor substrate
1
. In the DRAM area, lower electrodes
13
are formed to penetrate the interlayer insulating films
11
and
12
for conduction to the semiconductor substrate
1
. The lower electrodes
13
are covered with a dielectric film
14
and upper electrodes
15
. The lower electrodes
13
, dielectric film
14
and upper electrodes
15
constitute capacitors
16
that function as memory cells of the DRAM.
In the peripheral circuit area, tungsten plugs
17
are formed to penetrate the interlayer insulating films
11
and
12
for conduction to the semiconductor substrate
1
. On top of the interlayer insulating film
12
is another interlayer insulating film
18
that covers both the film
12
and the above-mentioned capacitors
16
. The tungsten plugs
17
conduct to aluminum wires
19
that are furnished on the interlayer insulating film
18
.
The semiconductor substrate
1
has impurity-diffused layers
20
formed at positions at which connecting to the lower electrodes
13
of the capacitor
16
, to the tungsten plugs
17
, and to the bit lines
10
. The impurity-diffused layer
20
is formed so as to sandwich each gate electrode
6
. On the semiconductor substrate
1
, the impurity-diffused layer
20
functions as a source drain region of each transistor; while the portions covered with the gate electrodes
6
serve as channels of transistors.
FIGS. 13A
to
13
E are explanatory views depicting how a DRAM hybrid IC is conventionally manufactured. By such a conventional method, a polysilicon layer
3
, a tungsten layer
4
and an oxide layer
5
are stacked one upon another all over the semiconductor substrate
1
. The stacked layers are patterned by photolithography and through etching to form gate electrodes
6
in the DRAM area and in the peripheral circuit area (FIG.
13
A).
From above the electrode gates
6
, impurities are implanted into the semiconductor substrate
1
to form an impurity-diffused layer
20
. A silicon nitride film
7
is formed all over the semiconductor substrate
1
so as to cover the impurity-diffused layer
20
and gate electrodes
6
(FIG.
13
B).
With the silicon nitride film
7
protected by a resist film (not shown) in the DRAM area, the silicon nitride film
7
in the peripheral circuit area is etched. The etching process causes the silicon nitride film
7
to form side walls of the gate electrodes
6
in the peripheral circuit area (FIG.
13
C). From above the silicon nitride film
7
, impurities are implanted into the semiconductor substrate
1
at a predetermined angle relative to the latter. As a result, the impurity-diffused layer
20
in the peripheral circuit area takes on an LDD (lightly doped drain) structure.
An interlayer insulating film
11
is deposited all over the semiconductor substrate
1
. Contact holes are formed by self-alignment techniques so as to communicate predetermined impurity-diffused layers
20
provided in the DRAM area. Bit lines
10
are then formed so as to conduct to the impurity-diffused layers
20
through the contact holes (FIG.
13
D).
An interlayer insulating film
12
is formed on the bit lines
10
and interlayer insulating film
11
. Contact holes are made through the interlayer insulating films
10
and
11
for conduction to predetermined impurity-diffused layers
20
provided in the DRAM area. Lower electrodes
13
are formed for conduction to the impurity-diffused layer
20
through the contact holes. A dielectric film
14
and an upper electrode
15
are formed to cover the lower electrodes
13
, whereby capacitors
16
are constituted (FIG.
13
E).
An interlayer insulating film
18
is then formed on the interlayer insulating film
12
. Tungsten plugs
17
are formed in the peripheral circuit area, and aluminum wires
19
that conduct to the tungsten plugs
17
are fabricated, whereby the conventional DRAM hybrid IC is constructed (see FIG.
12
).
In the DRAM hybrid IC, self-alignment techniques are used to make the contact holes in which to accommodate the bit lines
10
. For that reason, the topmost layer of the gate electrodes
6
in the DRAM area should preferably be an oxide film
5
. Meanwhile, the gate electrodes
6
in the peripheral circuit area should preferably have low levels of resistance. That is, the gate electrodes
6
in the peripheral circuit area should be so structured as to favor low resistance.
However, the conventional semiconductor manufacturing method involves manufacturing the gate electrodes
6
in the DRAM area and those in the peripheral circuit concurrently in the same step, as described above. This makes it practically impossible for the conventional method to make the gate electrodes
6
serving as DRAM components different in structure from the gate electrodes
6
acting as peripheral circuit components.
In the DRAM hybrid IC, the gate electrodes
6
are generally formed more densely in the DRAM area than their counterparts in the peripheral circuit area. For that reason, the gate electrodes
6
in the DRAM area need to be patterned more precisely than those in the peripheral circuit area during manufacture of the DRAM hybrid IC.
Conventionally, however, the gate electrodes
6
in the DRAM area and those in the peripheral circuit are to be formed in the same step. This makes it impossible for the conventional method to form, in separate steps, densely arranged gate electrodes
6
in the DRAM area and sparsely arranged gate electrodes
6
in the peripheral circuit area in such a manner that the respectively required levels of precision would be ensured for the gate electrode in th
Hachisuka Atsushi
Kasaoka Tatsuo
Soeda Shinya
Bowers Charles
Huynh Yennhu B.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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