Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-20
2002-07-09
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000
Reexamination Certificate
active
06417047
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-265205, filed Sep. 20, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a non-volatile semiconductor memory device and a manufacturing method thereof. Further, the present invention relates to the shape of end portions of a gate electrode formed in each of element regions insulated and isolated by embedded isolation regions. The present invention is applicable to a non-volatile semiconductor memory device of a batch-erasure type such as a NOR-type flash EEPROM or the like, and a memory-mounting logic integrated circuit.
In a semiconductor memory device having element regions insulated and isolated by embedded isolation regions, e.g., in a flash EEPROM, the film thickness of the gate oxide film in MOS transistors formed in a cell array region and that of MOS transistors formed in a peripheral transistor region are different from each other in order to optimize respectively performances of the MOS transistors formed in those regions.
In manufacture of a semiconductor memory device having element regions which are insulated and isolated by embedded isolation regions as described above, gate oxide films having different film thicknesses are formed. For example, gate oxide films of two different film thicknesses are formed. In this case, generally, a substrate is firstly-oxidized over its entire surface thereby to form a gate oxide film having a first film thickness, and the first gate oxide film is next remove partially in the region where a gate oxide film having a second film thickness is formed. Further, masking is carried out so that oxidation seeds might not be provided in the region where the first gate oxide film should remain formed. Thereafter, the second gate oxide film is formed.
In consideration of the relationship with a step of forming an isolation region, there may be various methods for forming gate oxide films having different film thicknesses as described above. For example, a flash EEPROM adopts a method in which a part of gate oxide films is formed before the step of forming isolation regions, and the other part of the gate oxide films is formed after the step of forming the isolation regions forming step.
Meanwhile, in a non-volatile semiconductor memory device having a two-layer gate structure (stacked gate) including a control gate and a floating gate, as represented by a flash EEPROM, there is a case that isolation is achieved by Shallow Trench Isolation (STI). If the floating gate falls into the isolation region at an edge of an active area which contacts with a STI region, electric field concentration on this edge causes variants of the memory cell characteristics and particularly variants of the tunnel current amount used for writing and erasure.
To reduce the variants of the tunnel current amount, a method has been taken in which a STI region is formed so that floating gates and element regions are formed with the positions of their end portions self-aligned with each other, after a tunnel oxide film for memory cells and a polysilicon film for floating gates are formed.
Also, the following method is adopted to maintain a sufficient capacitive coupling between a control gate and a floating gate. That is, the floating gate is formed of first and second polysilicon films. The second polysilicon film is formed on the first polysilicon film so that the second polysilicon film is directly connected with the first polysilicon film. Further, the second polysilicon film is extended over the STI regions.
These techniques are disclosed in, for example, K. Shimizu et al., “A Novel High-Density 5F
2
NAND STI Cell Technology Suitable for 256 Mbit and 1 Gbit Flash Memories” international ELECTRON DEVICES meeting 1997, WASHINGTON, D.C. Dec. 7-10, 1997, IEDM Technical Digest Paper pp 271-274.
Next, explanation will be made of steps of manufacturing the non-volatile memory, disclosed in the above reference.
This method is adopted to a case of a flash memory having a memory cell part and a peripheral circuit part.
FIGS. 1A
to
1
D shows steps of manufacturing the memory cell part, and
FIGS. 2A and 2B
shows steps of manufacturing the peripheral circuit part.
Note that the memory cell part has an array of stacked-gate-type cell transistors each having a control gate and a floating gate. In the stacked-gate-type cell transistor, the floating gate is comprised of two polysilicon films, and trenches for isolation are formed to be self-aligned with a polysilicon film as a first layer. A polysilicon film as a second layer is formed above the polysilicon film as the first layer.
At first, as shown in
FIG. 1A
, a tunnel oxide film (a tunnel oxide film for memory cells)
32
having a film thickness of 10 nm is formed on a silicon substrate
31
. A first polysilicon film
33
to form part of floating gates is formed on the tunnel oxide film. Next, as shown in
FIG. 1B
, a first polysilicon film
33
, a tunnel oxide film
32
, and a silicon substrate
31
are etched with use of a predetermined etching mask, thereby forming a plurality of grooves
34
in the silicon substrate
31
. These grooves
34
form STI for isolation. Also, the silicon substrate
31
is separated into a plurality of element regions.
Next, as shown in
FIG. 1C
, the grooves
34
are filled with an insulating film
35
for isolation. Further, a second polysilicon film
36
to form part of the floating gates is formed. Subsequently, a control gate
38
is formed with a gate insulating film
37
inserted thereunder, as shown in FIG.
1
D.
Meanwhile, with respect to the peripheral circuit part, the memory cell part is covered and protected by a photoresist not shown, in a stage in which the first and second polysilicon films
33
and
36
are formed, as shown in FIG.
2
A. Further, as shown in
FIG. 2B
, the second polysilicon film
36
and the first polysilicon film
33
are removed from the peripheral circuit part. Further, the tunnel oxide film
32
is removed therefrom. Thereafter, a polysilicon film for gate oxidation and gate electrodes is deposited again, thereby to form a gate oxide film
37
and gate electrodes
38
are formed.
At this time, if the gate electrodes
38
are formed to fall in the STI regions at edges of element regions, parasitic transistors are created among MOS transistors.
FIG. 3
is a cross-sectional view in which an edge part
3
of an element region surrounded by a circle mark in
FIG. 2B
is picked up and enlarged.
If the gate electrode
38
falls into the STI region a t edges of an element region, a parasitic transistor appears in the region B surrounded by a circle mark in the figure. If the parasitic transistor operates, a kink occurs in the subthreshold characteristic, thereby involving increase of the stand-by current. In particular, if the corner parts of the element region are not rounded, the field-effect concentration effect is increased so that the kink characteristic is emphasized.
To prevent this, it is advantageous to carry out a so-called rounding oxidation step of rounding the corner parts of the edge part A of the element region and of creating birds-beaks in the tunnel oxide film
32
, before STI regions are filled with the insulating film
35
during formation of STI, as shown in FIG.
4
. By optimizing the thickness of the oxide film in the rounding oxidation step, the extent to which the gate electrodes fall in the STI region can be restricted, for example, as shown in FIG.
5
.
The rounding oxidation step descried above has been proposed in the U.S. patent Ser. No. 09/527,870 “Semiconductor Device and manufacturing Method Thereof”. By the technique e proposed therein, it is possible to restrict the leakage current and the current consumption within a region where the gate voltage of the peripheral circuit transistors is low in a flash EEPROM which adopts the STI isolation structure. Accordingly, the subthreshold current ch
Pizarro-Crespo Marcos D.
Weiss Howard
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