Manufacturing method of a junction field effect transistor

Details Manufacturing method of a junction field effect transistor Manufacturing method of a junction field effect transistor

1999-09-17

2000-08-01

Fourson, George

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having junction gate

438194, 438285, 438569, 438572, 438590, H01L 21334

Patent

active

060965878

ABSTRACT:
A manufacturing method of a junction field effect transistor, promising a low ON resistance, high maximum drain current and linearity with a high transmission gain and also enabling the gate length to be reduced, makes a channel layer by sequentially epitaxially growing an undoped GaAs layer, n.sup.+ -type GaAs layer and n-type GaAs layer on a semi-insulating GaAs substrate via a GaAs buffer layer. Through an opening formed in a diffusion mask in form of a SiN.sub.x film on the n-type GaAs layer, Zn is diffused into the n-type GaAs layer to form a p.sup.+ -type gate region. From above the diffusion mask, a gate metal layer is deposited, and patterned to make a gate electrode in the opening of the diffusion mask in self-alignment with the p.sup.+ -type gate region.

REFERENCES:
patent: 4738934 (1988-04-01), Johnston, Jr. et al.
patent: 4804635 (1989-02-01), Young
patent: 5242846 (1993-09-01), Izumi et al.
patent: 5597744 (1997-01-01), Kamiyama et al.
patent: 5872031 (1999-02-01), Mishra et al.

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