Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-17
2001-04-17
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000
Reexamination Certificate
active
06218239
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a bottom plate of a capacitor. More particularly, the present invention relates to a manufacturing method of a crown structure of a capacitor in dynamic random access memory (DRAM).
2. Description of Related Art
With the steady improvement in integrated circuit (IC) fabrication, the dimensions of IC devices are greatly reduced. With a higher packing density, data transfer rate of IC products is higher while its functions and scope of applications continues to expand. In order to sustain the necessary growth, miniaturization of device dimensions in an IC chip has always been one major target in the semiconductor industry. This can be seen in the recent transition of manufacturing technologies from the VLSI to ULSI regime.
At present, one of the major products of integrated circuits in dynamic random access memory (DRAM). With the demand for packing more devices into a given wafer chip, available surface area of a capacitor for forming each memory cell is correspondingly reduced. The reducing of the available surface area causes electric charges stored in the capacitor insufficient and also causes data accessing difficult. That is, the data stored in the capacitor is easily lost and affected by other external factors. The repeating data refreshing operations are necessary for data safe storage, which increases the cost of operating the devices. Therefore, a demand for higher capacitance in a limited area of the device is continuously developed for storing more data. A method for higher capacitance of a capacitor is using a stacked structure or a crown structure of the capacitor for more surface area.
FIGS. 1A-1G
shows cross-sectional views of a conventional manufacturing method of a bottom plate of a capacitor in the DRAM. Referring to
FIG. 1A
, a metal oxide semiconductor (MOS) transistor
102
is formed in a substrate
100
. The MOS transistor
102
comprises a gate
102
a
, a pair of source/drain regions
102
b
and a spacer
102
c
. Next, an insulation oxide layer
104
is deposited over the substrate
100
, and then a photo resist layer
106
is formed over the insulation oxide layer
104
, in which a portion of the insulation oxide layer
104
is covered by the photo resist layer
106
.
Referring to
FIG. 1B
, the exposed portion of the insulation oxide layer
104
is then etched to form a capacitor node contact opening
108
therein. One of the source/drain regions
102
b
is then exposed, as shown in FIG.
1
B. Next, the photo resist layer
106
is removed.
Referring to
FIG. 1C
, a first polysilicon layer (not shown) is deposited over the insulation oxide layer
104
by, for example, a method of low-pressure chemical vapor deposition. The contact opening
108
is then filled with the polysilicon. The resistance of the first polysilicon layer is changed to about 500 &mgr;&OHgr;~1200 &mgr;&OHgr; by heavily doping with ions. Therefore, the first polysilicon layer can be conductive material for the capacitor. The first polysilicon layer above the insulation oxide layer
104
is eliminated by, for example, a method of chemical mechanical polishing or etching back and then a portion of the first polysilicon layer in the contact opening
108
is changed into a contact plug
108
a.
Next, referring to
FIG. 1D
, a second polysilicon layer
110
is formed over the insulation oxide layer
104
by, for example, a method of low-pressure chemical vapor deposition. The second polysilicon layer
110
is then heavily doped with ions. A photo resist layer
112
with a predetermined pattern is formed over the second polysilicon layer
110
, for example, the photo resist layer
112
has an opening
112
a
above the position of the plug
108
a
. The exposed portions of the second polysilicon layer
110
are etched to form some grooves therein, for example, a groove
114
above the contact plug
108
a
as shown in FIG.
1
E. After that, referring to
FIG. 1F
, the second polysilicon layer
110
is etched and changed to a crown-like bottom plate
110
b
by a photolithography precess. The crown-like bottom plate
110
b
is connected to the contact plug
108
.
The conventional manufacturing method of a polysilicon bottom plate is described above. After the formation of the bottom plate, material with a high dielectric constant such as tantalum pentoxide is then deposited over the formed structure, for forming the capacitor. However, the crown-like structure of the bottom plate easily results in the leakage phenomenon, which bring the bottom plate not effectively storing the charges, that is, the bottom can not work well to be a function of capacitance.
In light of the foregoing, there is a need to provide a bottom plate, which reduces the leakage phenomenon and possesses a reliable function of capacitance.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a manufacturing method of forming a bottom plate for a DRAM capacitor capable of high-density packing and having large charge storage capacity. Furthermore, the method is compatible with current IC fabrication techniques.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions, wherein the method comprises, at first, forming an insulation oxide layer on the substrate and the gate. Next, forming a contact opening in the insulation oxide layer, wherein one of the source/drain regions is exposed through the contact opening. Next, forming a contact plug in the contact opening. Next, forming a stop layer over the insulation oxide layer and the contact plug. Next, forming a first dielectric layer over the stop layer. Then, forming an opening which penetrates the first dielectric layer, the stop layer and the insulation oxide layer, wherein the bottom of the opening exposes a portion of the insulation oxide layer and the top portion of the contact plug. Finally, forming a crown-liked conductive plate over the insulation oxide layer and the contact plug, wherein the crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug, wherein the crown-like conductive plate is composed of tungsten silicide.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a manufacturing method of forming a bottom plate for a capacitor on a substrate, wherein the substrate comprises a MOS transistor having a gate and a pair of source/drain regions, wherein the method comprises: forming an insulation oxide layer on the substrate and the gate; forming a contact opening in the insulation oxide layer, wherein one of the source/drain regions is exposed through the contact opening; forming a contact plug in the contact opening; forming a stop layer over the insulation oxide layer and the contact plug; forming a first dielectric layer over the stop layer; forming an opening which penetrates the first dielectric layer, the stop layer and the insulation oxide layer, wherein the bottom of the opening exposes a portion of the insulation oxide layer and the top portion of the contact plug; and forming a crown-liked conductive plate over the insulation oxide layer and the contact plug, wherein the crown-liked conductive plate penetrates the insulation layer and the stop layer, wherein the bottom of the crown-like conductive plate is electrically connected to the contact plug, wherein the crown-like conductive plate is composed of a tungsten nitride layer and a tungsten layer on the tungsten nitride layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide fu
Chen Jacob
Huang Keh-Ching
Jung Tz-Guei
Lin Wen-Jeng
Abbott Barbara E.
Fourson George
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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