Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-03-20
2007-03-20
Chaudhari, Chandra (Department: 2891)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S529000, C257SE21636
Reexamination Certificate
active
10918433
ABSTRACT:
A manufacturing method for a transistor of an ESD protection device. First, the method forms basic elements on a semiconductor base. Next, a patterned resist layer is used as a mask to perform ion implantation in the emerged drain region so that the dopant can be implanted into the semiconductor base under the drain region to form an extended drain heavy-doped region. Then, the patterned resist layer is removed and a heat tempering processing is performed. Finally, a self-aligned salicide is formed on the surfaces of the polysilicon gate and the heavy-ion doped region. The invention utilizes an extended drain heavy-doped region as a resistance ballast between the drain contact and the polysilicon contact surface, which allows high current generated by ESD to be discharged in a more homogeneous way so as to prevent the ESD structure from being damaged.
REFERENCES:
patent: 6274911 (2001-08-01), Lin et al.
patent: 6514839 (2003-02-01), Ker et al.
patent: 6566717 (2003-05-01), Jung
Chaudhari Chandra
Grace Semiconductor Manufacturing Corporation
Rosenberg , Klein & Lee
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