Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-02-04
2001-06-12
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S527000
Reexamination Certificate
active
06245603
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device and, more particularly, to a MOSFET employing a pocket layer.
2. Description of Related Art
A metal oxide semiconductor field effect transistor (MOSFET) frequently employs a structure in which a region between a source-drain and a channel region has a lightly doped drain (LDD) layer that is an impurity layer of the same conductive type as the source-drain and of a low concentration and shallow junction in order to suppress short channel effect that poses a problem in reducing a gate length. However, when the gate length is 0.25 &mgr;m or less, it becomes difficult to suppress the short channel effect by the LDD structure alone. To overcome this difficulty, a structure employing a pocket layer is being used more frequently.
For producing the pocket layer, an impurity of a different conductive type from that of the source-drain must be supplied to a portion where a depletion layer extends under the channel region at the time of operation. For this purpose, ions are implanted aslant into a surface of a semiconductor substrate. After another ion implantation region, such as one that provides source-drain, is formed, the foregoing ion-implanted region is activated at the same time with another ion-implanted region to thereby form the pocket layer.
FIGS. 1 and 2
show sectional process views indicating a conventional process for forming a MOSFET. Referring to the sectional process views, the following will provide a brief explanation of a conventional process for forming a MOSFET having a pocket layer.
First, as shown in
FIG. 1A
, an oxide film, a poly-silicon film, a tungsten silicide film, and a nitride film are formed in this order on a p-type silicon substrate
410
. Then, the films of these four layers are subjected to patterning to selectively form a gate electrode
450
composed of a gate oxide film
411
, a poly-silicon
412
, and a tungsten silicide
413
, and a nitride film pattern
440
. In the next step, p-type impurity ions, e.g. BF
2
+
ions, are implanted into the p-type silicon substrate
410
at an angle with respect to the surface of the p-type silicon substrate
410
as indicated by arrows of
FIG. 1A
, using the nitride film pattern
414
and the gate electrode
450
as a mask, so as to form a p-type ion implantation region
420
.
Then, as shown in
FIG. 1B
, n-type impurity ions, e.g. As
+
ions, are implanted into the p-type silicon substrate
410
perpendicularly to the surface of the p-type silicon substrate
410
as indicated by arrows of
FIG. 1B
, using the nitride film pattern
440
and the gate electrode
450
as a mask, so as to form an n-type ion implantation region
444
. A dosage of the ions to be implanted is approximately one hundredth of a dosage of ions to be implanted for forming a source-drain layer
423
a
in FIG.
2
A.
In the next step, as illustrated in
FIG. 1C
, a side wall spacer
441
composed of a nitride film is selectively formed on side walls of the gate electrode
450
, the nitride film pattern
440
, and the gate oxide film
411
, then n-type impurity ions, e.g. As
+
ions, are implanted into the p-type silicon substrate
410
perpendicularly to the surface of the p-type silicon substrate
410
, using the side wall spacer
441
and the nitride film pattern
440
as a mask, so as to form an n-type ion implantation region
423
.
Subsequently, heat treatment is performed as shown in
FIG. 2A
to activate the ion implantation regions
420
,
444
, and
423
that have been formed so far in order to form a pocket layer
420
a
from the ion implantation region
420
, an LDD layer
444
a
from the ion implantation region
444
, and a source-drain layer
423
a
from the ion implantation region
423
. Then, an insulative interlayer film
415
formed of SiO
2
or the like is formed over the entire surface, and a contact hole
430
is opened above the source-drain layer
423
a.
Next, as illustrated in
FIG. 2B
, a contact layer
432
is embedded in the contact hole
430
, and a wiring layer
431
is formed on the contact layer
432
.
As described above, in the conventional process for forming a pocket layer, ions are implanted aslant with respect to the surface of the silicon substrate, the ion implantation region is formed in the portion where the depletion layer extends under the channel region at the time of operation, then the ion implantation regions are activated to thereby form the pocket layer.
However, when a design rule becomes, for example, 0.18 &mgr;m or less as microminiaturization advances, an interval between gate electrodes becomes smaller than a height of the gate electrodes. Therefore, implanting ions at an angle with respect to the surface of the silicon substrate causes a shadow effect to start to take place wherein impurity ions cannot be implanted in a shadow of an adjoining gate electrode. The shadow effect prevents the ion implantation region from being formed to cover the portion where the depletion layer spreads under the channel region during an operation. This means that the pocket layer cannot be formed. On the other hand, if a method is used wherein a time for diffusing the ion implantation layers after the formation of all the ion implantation regions is extended to form the pocket layer, then another ion implantation layer, e.g. the ion implantation layer to become the source-drain, excessively diffuses, resulting in deteriorated device characteristics.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a manufacturing method for a semiconductor device that permits a pocket layer to be securely formed in a semiconductor device of 0.18 &mgr;m or less in which the short channel effect becomes further noticeable.
To this end, according to the present invention, there is provided a manufacturing method for a semiconductor device wherein a gate insulating film and a gate electrode located on the gate insulating film are selectively formed on a surface of a first conductive type semiconductor substrate. Then, an impurity of the first conductive type is introduced perpendicularly to the surface of the semiconductor substrate, using the gate electrode as a mask to thereby form an ion implantation region of the first conductive type at a predetermined depth in the semiconductor substrate. The ion implantation region is diffused so that it extends and lies directly below a channel region that corresponds to the gate electrode, thus activating the ion implantation region. Thereafter, using the gate electrode as a mask, an impurity of a second conductive type is introduced at a predetermined depth from the surface of the semiconductor substrate so as to form an ion implantation region of the second conductive type. Then, the ion implantation region is activated to form a source and a drain of the second conductive type.
REFERENCES:
patent: 4985745 (1991-01-01), Kitahara et al.
patent: 6117735 (2000-09-01), Ueno
Nelms David
Nhu David
OKI Electric Industry Co., Ltd.
Rabin & Champagne, P.C.
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