Manufacturing method for semiconductor device

Details Manufacturing method for semiconductor device Manufacturing method for semiconductor device

2001-09-12

2003-05-13

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Radiation or energy treatment modifying properties of...

Reexamination Certificate

active

06562736

ABSTRACT:

RELATED APPLICATION DATA
The present application claims priority to Japanese Application(s) No(s). P2000-278349 filed Sep. 13, 2000, which application(s) is/are incorporated herein by reference to the extent permitted by law.
BACKGOUND OF THE INVENTION
The present invention relates to a manufacturing method for a semiconductor device, and more particularly to an annealing method by light irradiation after heteroepitaxial growth.
With a continuous reduction in minimum size of a bipolar integrated circuit formed on a semiconductor substrate, especially, a silicon substrate, it is more and more difficult to realize the cutoff frequency (f
T
), maximum oscillation frequency (f
max
), and propagation delay (&tgr;
pd
) of an associated transistor. This is due to the fact that parasitic factors related to the transistor increase with the reduction in minimum size.
The performance, especially, the cutoff frequency f
T
of a bipolar junction transistor (BJT) can be greatly improved by reducing the transit time of carriers in a base region and by reducing the area of a pn junction parasitically formed in the transistor to thereby minimize a parasitic capacity to an element.
The minimization of such parasitic factors tends to have a harmful effect on common-emitter current gain (h
fe
) and collector-emitter breakdown voltage (BV
CEO
). For example, base doping must be increased to maintain the collector-emitter breakdown voltage (BV
CEO
) with a decrease in base width. This causes not only a reduction in the common-emitter current gain (h
fe
), but also a reduction in time of exposure of this device to high temperatures during the subsequent processing. Accordingly, the cutoff frequency (f
T
) of an actual bipolar junction transistor is basically limited to about 20 to 30 GHz.
To solve this problem, it has recently been proposed to form a heterojunction as an emitter-base junction. By adopting a structure such that the emitter has a large bandwidth and the base has a small bandwidth, the injection of holes from the base to the emitter can be suppressed by the difference between these bandwidths, so that the injection efficiency of electrons to be injected from the emitter to the base can be relatively increased. As a result, the current gain of a bipolar transistor can be ensured and other advantages can also be obtained.
The combination in the heterojunction includes a method using an emitter having a large bandwidth and a method using a base having a small bandwidth. The former is a method using a material having a large bandwidth, such as GaAs, SiC, and Si as the emitter (see Tech. Dig., IEDM, pp. 186-193, 1987). The latter is a method using a material having a small bandwidth, such as Si—Ge mixed crystal as the base by MBE (molecular beam epitaxy), MOCVD (metalorganic chemical vapor deposition), etc. (see 1988 Spring 35th Applied Physics Related Joint Lecture Meeting, 29aZ12/I).
In particular, a heterojunction bipolar transistor (HBT) using a III-V compound semiconductor such as GaAs is being most aggressively researched and developed. In recent years, however, attention has been given to a HBT using SiGe as a IV—IV compound that can be fabricated on an inexpensive Si substrate.
Si has an electron affinity of 4.05 eV, and Ge has an electron affinity of 4.0 eV which is substantially the same as the electron affinity of Si. Further, Si has a bandgap of 1.1 eV, and Ge has a bandgap of 0.66 eV. It has been reported that a Si—Ge mixed crystal has a bandgap width intermediate of that of Si or Ge (see Band alignments of coherently strained Ge
x
Si
1
—
x
/Si heterostructures on <011> Ge
y
Si
1
—
y
substrates, Applied Physical Letters 48, Feb. 24, 1986). The combination of these materials allows the formation of a silicon heterojunction bipolar transistor having such a configuration that Si is used for the emitter, Ge or Ge—Si mixed crystal is used for the base, and Si is used for the collector.
In the transistor having the above configuration, a pn junction is formed at the interface between Si as the emitter and Si—Ge mixed crystal as the base. Accordingly, the energy barrier to holes is larger than that to electrons, so that the carriers diffused to flow in the pn junction are dominantly electrons. As a result, the emitter injection efficiency of the bipolar transistor using this heterojunction is largely increased.
Further, the injection of holes from the base to the emitter can be suppressed to eliminate the delay by the holes accumulated in the emitter. Further, a junction capacity between the emitter and the base can be reduced by a low concentration in the emitter. With these advantages, the above configuration is greatly effective in forming a high-speed bipolar transistor.
However, in the case of using a material having a small bandwidth, e.g., Si—Ge mixed crystal (Si
1
—
x
Ge
x
) formed by MBE, MOCVD, or LP-CVD, as the base, there is a problem of crystal defects such as dislocations and cracks when a Si—Ge mixed crystal layer having a considerably large thickness is deposited on a Si single-crystal substrate, because Si and Si—Ge mixed crystal have different lattice constants to cause lattice mismatch between the Si—Ge mixed crystal layer and the Si substrate. For this reason, a thick Si—Ge mixed crystal layer cannot be deposited on the Si substrate.
To increase the emitter injection efficiency, the change in bandwidth at the emitter-base junction must be steep. On the emitter side of the emitter-base junction, the injection of holes must be merely suppressed, so that the Si single-crystal layer as an emitter electrode on the Ge layer or Si—Ge mixed crystal layer as the base may be thin (e.g., 5 to 10 nm). Accordingly, epitaxial growth with no defects can be carried out between the base and the emitter.
However, there is a trade-off between base thickness and base resistance such that the latter increases with a decrease in the former. Accordingly, a required thickness of the base layer is about 10 to 100 nm. The thickness of the Si—Ge mixed crystal layer must be greater than or equal to the above required thickness of the base layer. Further, to ensure a sufficient bandgap difference between the emitter and the base, the composition x in Si
1
—
x
Ge
x
must be greater than or equal to 0.1. Accordingly, the thickness of the Si—Ge layer to be deposited on the Si substrate must be 50 to 300 nm.
It has been reported that when a Si
1
—
x
Ge
x
layer where x is near 0.5 having a thickness of 10 nm or more is formed on a Si substrate, dislocations are generated in the Si
1
—
x
Ge
x
layer (see SILICON MBE: FROM STRAINED-LAYER EPITAXY TO DEVICE APPLICATION: Journal of Crystal Growth 70 (1984), 444-451). Further, in the case of growing a Si
1
—
x
Ge
x
layer where x is greater than 0.5 having a thickness of 50 nm or more on a Si substrate, misfit dislocations due to lattice mismatch are generated in the Si—Ge layer to cause crystal defects in the base region.
The crystal defects become the recombination centers of carriers to reduce the emitter injection efficiency or cause penetration between the emitter and the collector. Thus, the crystal defects are a significant problem in obtaining normal transistor characteristics. At present, there has not yet been established any techniques for forming a single thick Si—Ge mixed crystal layer simultaneously satisfying the two requirements that the concentration of Ge is to be increased to ensure a sufficient bandgap difference between emitter and base and that a sufficient base thickness is to be ensured.
There have been reported various methods for eliminating or suppressing the propagation of dislocations in a heteroepitaxial grown layer on a Si substrate. A well known one of these methods is annealing after heteroepitaxial growth to be performed to reduce defects. For example, such annealing is described in the paper by J. W. Lee et al., Appl. Phys. Lett. 50, 31 (1987), the paper by Choi et al., Appl. Phys. Lett. 50, 992 (1987), and the paper by N. Chand et al., Appl. Phys. Lett. 49, 815 (1986).
It has been proved that annealing after h

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