Manufacturing method for reducing the thickness of a dielectric

Details Manufacturing method for reducing the thickness of a dielectric Manufacturing method for reducing the thickness of a dielectric

1998-12-01

2000-12-05

Wilczewski, Mary

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438488, 438532, 438770, 438787, 438250, 438253, 438393, 438396, H01L 2170

Patent

active

061566039

ABSTRACT:
The thickness of a capacitor dielectric layer is reduced by a manufacturing method. A first polysilicon layer is deposited on a substrate that has an isolation structure. Subsequently, nitrogen ions are implanted into the first polysilicon layer. The thickness of an oxide layer formed on the first polysilicon layer is determined by dosage of the implanted nitrogen ions. Next, the first polysilicon layer is patterned, so as to form a bottom electrode of the capacitor and expose a portion of the substrate. A thermal oxidation process is then performed to form an oxide layer, which is used as a gate oxide layer on the substrate and is also used as a dielectric layer in capacitor on the bottom electrode. Subsequently, a second polysilicon layer is deposited and patterned as an upper electrode of the capacitor on the capacitor dielectric layer. The thickness of the dielectric layer is affected by implanted nitrogen ions into the first polysilicon layer, so that the dielectric layer is thinner than the gate oxide layer. For this reason, the capacitance is increased, and simultaneously forming the gate oxide layer and the dielectric layer decreases the fabrication cycle time.

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patent: 5624871 (1997-04-01), Teo et al.
patent: 5814542 (1998-09-01), Nakajima

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