Manufacturing method for integrated circuit having...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S467000, C438S600000

Reexamination Certificate

active

07022572

ABSTRACT:
In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.

REFERENCES:
patent: 4543594 (1985-09-01), Mohsen et al.
patent: 4602354 (1986-07-01), Craycraft et al.
patent: 4646266 (1987-02-01), Ovshinsky et al.
patent: 4868616 (1989-09-01), Johnson et al.
patent: 4876220 (1989-10-01), Mohsen et al.
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 5301144 (1994-04-01), Kohno
patent: 5429968 (1995-07-01), Koyama
patent: 5477414 (1995-12-01), Li et al.
patent: 5568421 (1996-10-01), Aritome
patent: 5592419 (1997-01-01), Akaogi et al.
patent: 5621683 (1997-04-01), Young
patent: 5751012 (1998-05-01), Wolstenholme et al.
patent: 5835396 (1998-11-01), Zhang
patent: 5926415 (1999-07-01), Shin
patent: 5991193 (1999-11-01), Gallagher et al.
patent: 6005270 (1999-12-01), Noguchi
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6055180 (2000-04-01), Gudesen et al.
patent: 6088286 (2000-07-01), Yamauchi et al.
patent: 6128214 (2000-10-01), Kuekes et al.
patent: 6130835 (2000-10-01), Scheuerlein
patent: 6163048 (2000-12-01), Hirose et al.
patent: 6185121 (2001-02-01), O'Neill
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6324093 (2001-11-01), Perner et al.
patent: 6335890 (2002-01-01), Reohr et al.
patent: 6356477 (2002-03-01), Tran
patent: 6363000 (2002-03-01), Perner et al.
patent: 6420215 (2002-07-01), Knall et al.
patent: 6445613 (2002-09-01), Nagai
patent: 6462979 (2002-10-01), Schlösser et al.
patent: 6473328 (2002-10-01), Mercaldi
patent: 6477077 (2002-11-01), Okazawa
patent: 6490194 (2002-12-01), Hoenigschmid
patent: 6498747 (2002-12-01), Gogl et al.
patent: 6515888 (2003-02-01), Johnson et al.
patent: 6522594 (2003-02-01), Scheuerlein
patent: 6525953 (2003-02-01), Johnson
patent: 6541312 (2003-04-01), Cleeves et al.
patent: 6545898 (2003-04-01), Scheuerlein
patent: 6567287 (2003-05-01), Scheuerlein
patent: 6584006 (2003-06-01), Viehmann
patent: 6611453 (2003-08-01), Ning
patent: 6618295 (2003-09-01), Scheuerlein
patent: 6631085 (2003-10-01), Kleveland et al.
patent: 6703861 (2004-03-01), Ting
patent: 6704224 (2004-03-01), Natori
patent: 6794726 (2004-09-01), Radens et al.
patent: 6859408 (2005-02-01), Porter et al.
patent: 2002/0028541 (2002-03-01), Lee et al.
patent: 2003/0128581 (2003-07-01), Scheuerlein et al.
patent: 2004/0002184 (2004-01-01), Cleeves
patent: 2004/0100852 (2004-05-01), Scheuerlein et al.
patent: 2004/0119122 (2004-06-01), Ilkbahar et al.
patent: 2004/0124415 (2004-07-01), Walker et al.
Graaf De C., and N. Johan Knall, “A Novel High-Density Low-Cost Diode Programmable Read Only Memory,” 1996 IEEE, IEDM Technical Digest, San Francisco, CA, Dec. 8-11, 1996, pp. 189-192.
Naji, Peter K., and N. Johan Knall, “A 256kb 3.0V ITIMTJ Nonvolatile Magnetoresistive RAM,” 2001 IEEE ISSCC, Feb. 6, 2001, Paper 7.6, and associated slide handouts, 35 pages.
Greene, Jonathan, and N. Johan Knall, “Antifuse Field Programmable Gate Arrays,” Proceedings of the IEEE, vol. 81, No. 7, New York, Jul. 1993, pp. 1042-1056.
Takeuchi, Ken, and N. Johan Knall, “A Negative VthCell Architecture for Highly Scalable, Excellently Noise-Immune, and Highly Reliable NAND Flash Memories,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, pp. 675-684.
Nishihara, Toshiyuki, and N. Johan Knall, “A Quasi-Matrix Ferroelectric Memory for Future Silicon Storage,” IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov., 2002, pp. 1479-1484.
Sugibayashi, Tadahiko, and N. Johan Knall, “A 30-ns 256-Mb DRAM with a Multidivided Array Structure,” IEEE Journal of Solid-State Circuits, vol. 28, No. 11, Nov., 1993, pp. 1092-1098.
Evans, Robert J., and N. Johan Knall, “Energy Consumption Modeling and Optimization for SRAM's,” IEEE Journal of Solid-State Circuits, vol. 30, No. 5, May, 1995, pp. 571-579.

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