Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-08-18
1999-06-15
Trinh, Michael
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438301, 438307, 438558, H01L 21336, H01L 2122
Patent
active
059131233
ABSTRACT:
A method for manufacturing a deep-submicron P-type metal-oxide semiconductor shallow junction utilizes an electron terminal structure with a base covered by a layer containing boron, germanium, and silicon. This layer containing boron, germanium, and silicon ("B--Ge--Si") is used as a shield during ion implanting and as an impurity ion source to form a high diffusion ion concentration at a shallow junction of the semiconductor base or substrate. The B--Ge--Si layer can be thoroughly removed using selective corrosive erosion. Due to the simplicity of this invention's manufacturing process, it can be used for deep-submicron PMOS component production, and thus, it has great practical value.
REFERENCES:
patent: 4640721 (1987-02-01), Uehara et al.
patent: 5281552 (1994-01-01), King et al.
patent: 5407847 (1995-04-01), Hayden et al.
patent: 5443994 (1995-08-01), Solheim
patent: 5500391 (1996-03-01), Bevk et al.
patent: 5521108 (1996-05-01), Rostoker et al.
patent: 5668027 (1997-09-01), Hashimoto
Chao Jien-Sheng
Chen Liang-Po
Lin Horng-Chih
National Science Council
Trinh Michael
LandOfFree
Manufacturing method for deep-submicron P-type metal-oxide semic does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Manufacturing method for deep-submicron P-type metal-oxide semic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method for deep-submicron P-type metal-oxide semic will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-409905