Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-05-31
2008-05-20
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S210000, C438S253000, C438S254000, C438S255000, C438S256000, C438S381000, C438S393000, C438S394000, C438S395000, C438S396000, C257SE21641
Reexamination Certificate
active
07374992
ABSTRACT:
The present invention provides a manufacturing method for an integrated semiconductor structure comprising the steps of: providing a semiconductor substrate having a plurality of gate stacks in a memory cell region and at least one gate stack in a peripheral device region; forming caps made of one or more layers of a cap material over said plurality of gate stacks in said memory cell region and over said at least one gate stack in said peripheral device region; forming a first contact hole between two neighboring gate stacks in said memory cell region; depositing a first protective layer over said memory cell region and peripheral device region; exposing said cap of said at least one gate stack in said peripheral device region; modifying said exposed cap of said at least one gate stack in said peripheral device region in a process step wherein said first protective layer acts as a mask in said memory cell region; forming a second protective layer over said modified cap in said peripheral device region; partly removing said first and second protective layer in order to bring said first and second protective layer to about a same upper level; removing said first protective layer from said first contact hole; forming at least one another contact hole in said peripheral device region, said at least one another contact hole exposing another contact area which is located either adjacent to said gate stack or in said gate stack in said peripheral device region; and filling said contact hole and said at least one another contact hole with a respective contact plug.
REFERENCES:
patent: 6506647 (2003-01-01), Kuroda et al.
patent: 2002/0042172 (2002-04-01), Kuroda et al.
patent: 2004/0029323 (2004-02-01), Shimizu et al.
patent: 2006/0189051 (2006-08-01), Kim
patent: 102004042167 (2006-03-01), None
patent: 100585180 (2006-05-01), None
German Examination Report dated Jan. 18, 2007.
Baars Peter
Goldbach Matthias
Muemmler Klaus
Eschwailer & Associates LLC
Lebentritt Michael
Lee Kyoung
Oimonda AG
LandOfFree
Manufacturing method for an integrated semiconductor structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Manufacturing method for an integrated semiconductor structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method for an integrated semiconductor structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3985313