Manufacturing method for a recessed channel array transistor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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Details

C438S589000, C257S330000, C257SE21384, C257SE21419, C257SE21428, C257SE21626, C257SE21640

Reexamination Certificate

active

11105580

ABSTRACT:
The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

REFERENCES:
patent: 6930062 (2005-08-01), Hyun et al.
patent: 7060574 (2006-06-01), Kim et al.
patent: 2002/0081799 (2002-06-01), Kim
patent: 2005/0042833 (2005-02-01), Park et al.

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