Manufacturing method for a capacitor in an integrated storage ci

Details Manufacturing method for a capacitor in an integrated storage ci Manufacturing method for a capacitor in an integrated storage ci

1999-05-14

2000-10-03

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, H01L 218242

Patent

active

061272205

ABSTRACT:
On a carrier a layer sequence is applied which contains alternatingly layers made of a first conducting material and a second material in which both materials are different from a carrier material. An opening is made in the layer sequence, which is filled with a conducting material so that a central supporting structure is produced. Then the layer sequence is structured corresponding to the dimensions of a capacitor and the layers made of the second material are removed selectively, so that a first capacitor electrode is formed. The layer sequence may have especially p.sup.+ -/p.sup.- silicon layers or silicon/germanium layers. An etch-stop layer can also be incorporated as the lowest or second-lowest layer.

REFERENCES:
patent: 5155657 (1992-10-01), Oehrlein et al.
patent: 5196365 (1993-03-01), Gotou
patent: 5716884 (1998-02-01), Hsue et al.
Journal of the Electrochemical Society, vol. 137, No. 11, Nov. 1990 (Seidel et al.), pp. 3626-3632, "Anisotropic Etching of Crystalline Silicon in Alkaline Solutions".
International Electron Devices Meeting, Dec. 1988, pp. 592-595, 3-Dimensional Stacked Capacitor Cell for 16M and 64M Drams (Ema et al.).

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