Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-14
2001-03-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S396000, C438S970000
Reexamination Certificate
active
06204119
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a manufacturing method for a capacitor in an integrated memory circuit.
Capacitors are needed in a number of integrated semiconductor circuits, for example in DRAM circuits or A/D converters. In many cases, the problem arises to realize a high capacitance sufficient for requirements with a minimum space being occupied. That problem is especially severe in DRAM circuits in which each memory cell has a memory capacitor and a selection transistor, while the space available for a memory cell is being continuously reduced. At the same time, the memory capacitors must retain a certain minimum capacitance for reliable storage of the charge and distinguish ability of the information to be read. That minimum capacitance is considered to be 25 fF at the present time.
In order to realize maximum capacitance of the memory capacitor with a given space requirement, among others, trench capacitors are known in which capacitor electrodes are disposed along side walls of a trench located in the substrate.
Another cell concept is the so-called stacked capacitor cell in which the capacitor is disposed as a stacked capacitor above the corresponding selection transistor and mostly also above the bit line. As a result thereof, the entire base area of the cell can be utilized for the capacitor and merely sufficient insulation to the neighboring memory capacitor needs to be ensured. That concept has the advantage of being highly compatible with a logic process.
A memory cell configuration with a stacked capacitor is known from European Patent 0 415 530 B1. The stacked capacitor includes a polysilicon structure with several polysilicon layers disposed essentially parallel on top of one another and connected to one another with a side support. Those layers, which are disposed in the manner of radiator ribs, lead to a significant enlargement of the surface of the polysilicon structure in comparison to the projection of the polysilicon structure onto the substrate surface. The polysilicon structure is formed by alternating deposition of polysilicon layers and selectively etchable silicon oxide or carbon layers on the surface of the substrate, structuring of those layers, producing side coverage (spacers made of polysilicon) on at least one side of the layer structure and selective etching of the silicon oxide or carbon layers. The polysilicon structures are doped with arsenic. Then, a silicon oxide as a capacitor dielectric is formed by thermal oxidation deposited on a cell plate made of doped polysilicon.
Another manufacturing method for such a multilayer stacking capacitor (called a fin-stacked capacitor) is described in European Patent Application EP 0 779 656 A2. A layer structure of alternating p
+
/p
−
-doped silicon layers is produced. Each layer structure is divided into two separate partial areas by etching an opening all the way to the underlying substrate and a capacitor is formed from each partial area, which then has a supporting structure on three sides.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a manufacturing method for a capacitor in an integrated memory circuit, especially in a DRAM circuit, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type, which can be performed easily and which is distinguished by high process reliability.
With the foregoing and other objects in view there is provided, in accordance with the invention, a manufacturing method for a capacitor in an integrated memory circuit, which comprises initially forming a first layer formed of a conducting first material and an auxiliary layer acting as an etch-stop, on a carrier which may contain an insulation layer with a connection embedded therein. Then, a sequence of layers is produced on the auxiliary layer. The sequence is formed alternatingly of a layer of the first material and a layer of a second material. The second material can be selectively etched with respect to the first material. The sequence of layers, the auxiliary layer and the first layer are structured all the way to the carrier so that a layer structure with sides is formed. A supporting structure is produced on these sides, which reach all the way down to the carrier, from a conducting material which covers the sides. Then, an opening is formed which extends through the sequence of layers inside the layer structure, with the aid of anisotropic etching that is selective with respect to the auxiliary layer. The auxiliary layer and the layers of the second material are removed with selective etching to the first material and to the supporting structure. Different etching processes can be used for the different materials in any arbitrary sequence. The layers can be removed in a single etching process with proper selection of the auxiliary layer and of the second material. In each case, etching processes with an isotropic component are used, so that only the layers of the first material and the supporting structure remain and form the first capacitor electrode. The free-lying surfaces of the layers made of the first material and the supporting structure are provided with a capacitor dielectric. A second electrode is formed on the surface of the capacitor dielectric.
High stability is ensured when etching the second material and the auxiliary layer by etching the opening inside the layer structure, because the supporting structure is formed on all of the outer sides of the layer structure. The layers made of the first material can therefore be very thin, for example, 20 to 50 nm.
The auxiliary layer makes it possible to produce an opening in the inner layer structure and simultaneously have very high process reliability because it provides a reliable etch-stop above or on the first conducting layer. Without the auxiliary layer, there is a danger of etching through the first conducting layer in the region of the opening. Since this opening, in general, covers the contact hole entirely or partially (as a connection of the first capacitor electrode), removal of the first layer would lead to a lack of or to a very poor connection of the first capacitor electrode. In other applications, etching of or etching through the first conducting layer can lead to worsened electrical properties or to damage of the structures lying underneath.
The etching process used for the production of the opening should be merely anisotropic and have sufficient selectivity with respect to the auxiliary layer. The etch rates of the first and second material do not have to be the same, since the supporting structure does not have to be etched uniformly with the layer structure.
The layers of the first material and the supporting structure can be formed from p
+
-doped silicon with a dopant concentration >10
20
cm
−3
and the layers of the second material can be formed from p
−
-doped silicon with a dopant concentration <10
19
cm
−3
. It is known from an article by H. Seidel et al., in the Journal of the Electrochemical Society, Volume 137 (1990), page 3626 ff. that p-doped silicon can be etched selectively with respect to p
+
-doped silicon. Etch rate differences up to a factor of 1000 are achieved between silicon with a boron doping of >10
20
cm
−3
and silicon with a boron doping of <10
19
cm
−3
.
p
+
-Doped silicon and p
−
-doped silicon can be deposited in the same reactor, as a result of which the sequence of layers can be realized without changing the installation, by merely switching the process parameters. This results in a significant simplification of the process.
In accordance with another mode of the invention, the layers of the first material may be doped silicon, and the layers of the second material may be a germanium-containing material, for example pure germanium or germanium and silicon. When the layers are formed from germanium and silicon, the germanium content is preferably between 10% and 100%. The silicon content lies bet
Franosch Martin
Honlein Wolfgang
Lange Gerrit
Lehmann Volker
Reisinger Hans
Greenberg Laurence A.
Kennedy Jennifer M.
Lerner Herbert L.
Niebling John F.
Siemens Aktiengesellschaft
LandOfFree
Manufacturing method for a capacitor in an integrated memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Manufacturing method for a capacitor in an integrated memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method for a capacitor in an integrated memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2449717