Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1993-09-22
1997-04-08
Thomas, Tom
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
364490, H01L 2170
Patent
active
056187440
ABSTRACT:
According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
REFERENCES:
patent: 4516312 (1985-05-01), Tomita
patent: 5081059 (1992-01-01), Ohe
patent: 5322438 (1994-06-01), McNutt et al.
Fujine Eiji
Itazu Kazushige
Kamiya Yoshihiro
Kawazoe Kazunori
Murakami Takako
Fujitsu Ltd.
Fujitsu VLSI Ltd.
Thomas Tom
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