Manufacturing a capacitor electrode in a semiconductor device

Details Manufacturing a capacitor electrode in a semiconductor device Manufacturing a capacitor electrode in a semiconductor device

1999-09-16

2001-04-03

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000, C438S396000, C438S397000, C438S009000

Reexamination Certificate

active

06211009

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention deals, in general, with semiconductor devices.
2. Description of the Related Art
With reference to the figures, and in particular with reference now to
FIG. 1E
, shown is semiconductor device storage capacitor structure
100
. Those skilled in the art will recognize that semiconductor device storage capacitor structure
100
is often utilized as part of integrated circuit devices such as dynamic random access memory (DRAM) cells, such as those composed of a metal oxide semiconductor (MOS) transistor and a storage capacitor (not shown), or as part of microprocessors (not shown).
Conventional techniques used to form semiconductor device storage capacitor structure
100
require the use of several discrete production tools. “Production tool” is a term of art used to indicate a stand alone machine that performs a related series of operations upon a semiconductor wafer during semiconductor device manufacturing. Those skilled in the art will recognize that each production tool typically performs only a finite number of manufacturing steps.
FIG. 1A
depicts a structure typically produced by the use of a first production tool. Illustrated in
FIG. 1A
, formed on a silicon
1
substrate (not shown) via techniques well known in the art, are field oxide isolation region
104
, gate insulating film (not shown), gate electrodes
106
, and layer
101
of insulating material
102
covering gate electrodes
106
. (
1
Silicon is defined herein to mean at least In situ phosphorous doped polysilicon, phosphorous deposited polysilicon, non-doped polysilicon, and amorphous silicon: consequently, reference to silicon herein is intended to encompass at least the foregoing-listed types of silicon.).
FIG. 1B
shows a structure resulting from the sequential use of a second, third, fourth, and fifth production tool to modify the structure of FIG.
1
A. Depicted in
FIG. 1B
is a structure having layer
107
of photoresist film
109
deposited on layer
101
of insulating material
102
. Illustrated is that contact hole
110
has been formed to extend through layer
107
of photoresist film
109
and layer
101
of insulating material
102
. Photolithography masking (hereby referred to as masking) and Reactive Ion Etching (hereby referred to as Plasma Etching) techniques are used to form contact hole
110
in a manner well known to those within the art. Contact hole
110
can be used to form electrical contact with a memory cell as described below.
FIG. 1C
illustrates a structure resulting from the sequential use of a sixth, seventh, eighth, ninth, and tenth production tool to modify the structure of FIG.
1
B. Shown in
FIG. 1C
is that layer
107
of photoresist film
109
has been removed, layer
113
of silicon
114
has been formed on layer
101
of insulating material
102
, and that desired-shape mask
116
formed from photoresist film
109
. Chemical Vapor Deposition (hereby referred to as CVD) is typically used to form added layer
113
of silicon
114
in a manner well known to those in the art. Desired-shape mask
116
is formed on added layer
113
of silicon
114
via a process well known to those within the art.
FIG. 1D
shows a structure resulting from the use of an eleventh and twelfth production tool to modify the structure shown in FIG.
1
C.
FIG. 1D
depicts storage capacitor solid-cylinder electrodes
118
of silicon
114
. Storage capacitor solid-cylinder electrodes
118
are formed on the silicon film via plasma etching in a manner well known to those within the art. Note that in forming solid-cylinder electrodes
118
of silicon
114
, desired-shape mask
116
of photoresist material
109
has been removed.
FIG. 1E
depicts a structure resulting from the use of a thirteenth, fourteenth, and fifteenth production tool to modify the structure shown in FIG.
1
D.
FIG. 1E
illustrates capacitor structure
100
where an insulating film
120
formed on the entire surface of the current structure with a subsequent layer
121
of silicon
114
being formed on insulating film
120
. The subsequently formed layer
121
of silicon
114
acts as an opposing electrode to the previously developed solid-cylinder capacitor electrode
118
thus completing capacitor structure
100
.
While capacitor structure
100
has proved very useful, those skilled in the art will recognize that capacitor structure
100
does have several associated disadvantages. For example, in order to achieve a larger capacitance in storage capacitor structure
100
, the surface area of at least one of the opposing electrodes must be increased. In conventional memory cell structures within an integrated circuit (a typical application of capacitor structure
100
), an increase in surface area is achieved by an increase in height of solid-cylinder capacitor electrode
118
(e.g., height increase ‘h’ as depicted in FIG.
1
D). Those skilled in the art will appreciate that a primary reason electrode height is the parameter increased instead of electrode length and/or width is that space constraints in typical semiconductor devices make increases in electrode length and/or width impracticable. In addition, another disadvantage is increases in electrode height are limited by the fact that as electrode height is increased, attaining acceptable electrode profile through plasma etching becomes increasingly difficult, and the fact that increased electrode height results in severe topography
2
for following layers and processes. Such severe topography results in problems for photolithography masking and plasma etching of future layers. (
2
Topography in semiconductor terms can be defined as height difference between high and low spots on the wafer surface. It is desirable to keep height difference as small as possible. Severe topography is defined as a large height difference.)
In an effort to avoid the noted disadvantages associated with capacitor structure
100
, a related-art attempt has been made to achieve increased surface area between opposing capacitor electrodes by avenues other than that of increasing a bottom electrode height of a solid-cylinder electrode
118
as was described above. The attempt has focused on changing the shape of a semiconductor device capacitor bottom electrode to that of hollow-cylinder capacitor structure
200
shown in FIG.
2
F. Conventional techniques used to form semiconductor device hollow-cylinder capacitor structure
200
require use of several production tools.
FIG. 2A
depicts a structure typically produced by the use of a first production tool. Depicted in
FIG. 2A
are two layers
202
,
204
of oxide
205
formed with an intermediate layer
206
of silicon
114
using CVD techniques. Illustrated is that a mask
208
of photoresist film
109
is placed above layer
202
of oxide
205
.
FIG. 2B
shows a structure resulting from the use of a second production tool to modify the structure of FIG.
2
A. Subsequent to the production of the structure shown in
FIG. 2A
, plasma etching techniques are used to obtain an layer
203
of oxide
205
having a desired shape as shown in FIG.
2
B.
FIG. 2C
shows a structure resulting from the use of a third production tool to modify the structure of FIG.
2
B. Subsequent to the production of the structure shown in
FIG. 2B
, mask
208
of photoresist film
109
is removed leaving the structure
212
shown in FIG.
2
C.
FIG. 2D
shows a structure resulting from the use of a fourth production tool to modify the structure of FIG.
2
C. Subsequent to the production of the structure shown in
FIG. 2C
, CVD techniques are used to form added layer
214
of silicon
114
on the structure
212
shown in
FIG. 2C
, resulting in the structure
216
shown in FIG.
2
D.
FIG. 2E
shows a structure resulting from the use of a fifth production tool to modify the structure of FIG.
2
D. Subsequent to the production of structure
216
shown in
FIG. 2D
, structure
216
shown in
FIG. 2D
is exposed to plasma etching which anisotropically etches flat portions of layer
214
of silicon
114
away,

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