Manufacture or trench-gate semiconductor devices

Details Manufacture or trench-gate semiconductor devices Manufacture or trench-gate semiconductor devices

2002-06-04

2003-02-18

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S589000

Reexamination Certificate

active

06521498

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a method of manufacturing a vertical power transistor trench-gate semiconductor device of the type having a plurality of transistor cells, each transistor cell being surrounded by a trench-gate structure comprising a trench extending into a semiconductor body with gate material in the trench and a gate insulating layer between the trench and the gate material, and each transistor cell having an annular source region adjacent an upper part of the trench-gate structure and separated from a drain region by a channel-accommodating body region adjacent the trench-gate structure. The invention also relates to semiconductor devices of this type manufactured by such a method.
DESCRIPTION OF THE RELATED ART
In a method of manufacturing a device of the above-defined type which is known from United States patent U.S. Pat. No. 5,378,655, the method includes forming the source regions so as to be self-aligned to the trench-gate structures. This self-alignment is achieved by the disclosed and taught method summarised as follows. A trench is etched through a window in a mask on a semiconductor body. After removing the mask, gate material is provided in the trench and then an upper portion of the gate material is oxidised to form a trench-gate structure which has an insulating cap on the gate. The insulating cap is then caused to form a step which protrudes from the adjacent semiconductor surface. A layer is then provided over the surface structure and then etched to leave a side wall spacer in the trench-gate step. The spacer is then used to define the source region which is thus formed to be self-aligned to the trench-gate structure.
By using such techniques as disclosed in U.S. Pat. No. 5,378,655, the number of photolithographic masking steps which require separate alignment can be reduced and compact cellular device structures can be formed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an alternative and advantageous method of forming the source regions self-aligned to the trench-gate structures.
According to the present invention there is provided a method as defined in claim
1
. The method is characterised by the steps of:
(a) forming on a surface of the semiconductor body a first mask of a first material with first windows, each said first window having a mid-point path coincident with a mid-point path of the location of a said trench;
(b) providing in each first window a U-shaped section layer of an insulating second material, the layers of second material being provided after the trench-gate structures are formed, each layer of second material having upright portions on the side walls of the first window and a base portion which provides a gate insulating overlayer on the gate material of a said trench-gate structure;
(c) removing the first mask and then forming spacers, each spacer having a vertical surface which is aligned with the location of a surface of a said upright portion of the layer of second material and each spacer having a horizontal base surface;
(d) using the spacers to form the annular source regions with the lateral extent of the source regions from the trench-gate structures being determined by the lateral extent of the base surface of the spacers; and
(e) providing a source electrode to contact the source regions and the body regions adjacent the source regions.
In the method of the present invention, the upright portions of the U-shaped section layers provide well-defined steps for the spacers used to form the source regions. Also, providing a gate insulating overlayer on the gate material by means of the base portion of the U-shaped section layers is preferable to providing this overlayer by oxidising the gate material, which can involve so-called bird's beak problems. Preferred features of the present invention are indicated as follows.
The trenches may be etched using a mask of said first material as defined in claim
2
or claim
3
. These mask windows may then be widened so that the gate insulating layers have horizontal extensions on the semiconductor body surface which remain when the first mask is removed as defined in claim
3
, these horizontal extensions advantageously protecting the gate insulation near the top of the trenches during this removal of the first mask.
As defined in claim
5
, a mask of the first material may first have preceding U-shaped section layers provided in its windows with a central part of the base portion of these layers being removed to provide etch windows for the trenches after which the remainder of the preceding layers is removed, the mask of the first material then being used for providing the U-shaped section layers which define steps for the spacers used to form the source regions. In this way, starting from one mask, a two-stage self-aligned process may provide well-defined narrow trenches and then well-defined source regions.
As defined in claims
2
,
4
or
7
, each spacer vertical surface may be aligned with an outer surface of one of the upright portions of the second material. The spacers may be formed with a third material present in the U-shaped section layers as defined in claim
8
. Otherwise, the third material may be removed before forming the spacers of an insulating material such that further spacers are also formed against the inner surfaces of the upright portions and merge to cover the base portions of the U-shaped section layers as defined in claim
9
. Such merged spacers forming a further insulating layer on top of the gate insulating U-cup base advantageously reduces gate-source capacitance. In cases where the spacers are formed against the U-shaped section second layer uprights, the first mask may be silicon dioxide and the second layer may be silicon nitride as defined in claim
10
; in this case the high etch selectivity of the oxide with respect to the nitride advantageously assists good definition of the nitride uprights when the oxide mask is removed.
As an alternative to forming the spacers against the U-shaped section second layer uprights, the U-shaped section layers may be filled with a third material and the upright portions may be removed when the first mask is removed so that the spacers are formed against the third material as defined in claim
11
; in this case the first mask material and the second layer material may both be silicon dioxide.
The source regions may be formed by etching upper regions of the semiconductor body of a suitable conductivity type using the spacers as a mask as defined in claim
13
. The spacers may then be etched as defined in claim
14
to advantageously expose top surfaces as well as side surfaces of the source regions for improved contact by the source electrode. Preferably the upper regions which are to be etched to form the source regions are formed by dopant implantation and diffusion after removing the first mask as defined in claim
15
. Forming these upper regions at this late stage in the process is advantageous for thermal budget reasons.


REFERENCES:
patent: 5378655 (1995-01-01), Hutchings et al.
patent: 5726088 (1998-03-01), Yanagiya et al.
patent: 5918114 (1999-06-01), Choi et al.
patent: 5972741 (1999-10-01), Kubo et al.
patent: 6096608 (2000-08-01), Williams

Affiliated with

Also associated with

Rating

Manufacture or trench-gate semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Manufacture or trench-gate semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacture or trench-gate semiconductor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3161317