Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-28
2002-04-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S555000, C438S259000, C438S700000
Reexamination Certificate
active
06368921
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to methods of manufacturing a trench-gate semiconductor device, for example an insulated-gate field-effect power transistor (commonly termed a “MOSFET”) or an insulated-gate bipolar transistor (commonly termed an “IGBT”). The invention also relates to semiconductor devices manufactured by such a method.
Such trench-gate semiconductor devices are known having source and drain regions of a first conductivity type separated by a channel-accommodating body region of the opposite second conductivity type. An advantageous method of manufacture is disclosed in United States patent U.S. Pat. No. 5,378,655 (our reference PHB 33836), in which the formation of the source region is self-aligned with the trench (also termed “groove”) which comprises the gate. The self-alignment is achieved by forming a second mask from a first mask, by the provision of side-wall extensions on the first mask. These side-wall extensions act as self-aligned spacers. The whole contents of U.S. Pat. No. 5,378,655 are hereby incorporated herein as reference material. By using such techniques as disclosed in U.S. Pat. No. 5,378,655, the number of photolithographic masking steps which require separate alignment can be reduced and compact cellular device structures can be formed.
Trench-gate semiconductor devices are also known in which the channel-accommodating body region is of the same, first conductivity type as the source and drain regions. In this case, the conductive channel is formed by charge-carrier accumulation by means of the trench-gate. Similar considerations arise with respect to the doping of the regions and the etching of the trench, as in the more usual device in which the channel-accommodating region is of the opposite, second conductivity type.
SUMMARY OF THE INVENTION
It is an aim of the present invention to modify the manufacture of trench-gate semiconductor devices so as to permit the use of self-aligned masking techniques while providing a simpler process with good reproducibility for device structures that can be even more compact.
According to the present invention there is provided a method of manufacture wherein a source region is formed by introducing dopant of a first conductivity type into an area of the body region via a mask window, diffusing the dopant to form a surface region of the first conductivity type that extends laterally below the mask at a distance beyond the masking edge of the window, and then etching the body at the window to form a trench for the trench-gate with a lateral extent that is determined by the etching of the body at the masking edge of the window, a portion of the surface region being left to provide the source region adjacent to the trench.
The method as set out in claim
1
includes quite different steps (a) to (f) from the method steps of U.S. Pat. No. 5,378,655. In particular, by diffusion of the dopant of the first conductivity type laterally below the trench-etch mask over a distance beyond the masking edge of the window, the source region is defined in a self-aligned manner with respect to the trench, without requiring any side-wall extension on the mask at the window. The absence of side-wall extensions can permit a more compact device structure. The etch edge definition for the trench can be better controlled by using the masking edge of a well-defined mask, as compared with the less well defined edges that tend to result with a side-wall extension (particularly if the extensions are kept short to provide a compact device). Side-wall extensions are conveniently formed of doped polycrystalline silicon or of silicon dioxide, which the inventors find to be often etched slightly by the etchant used for the trenches. In the method in accordance with the present invention, the mask can easily be chosen to comprise a material, for example silicon nitride, that is not etched by the etchant used for the trenches, and it can be well-defined using usual photolithographic and etching techniques. Even more important is the fact that any slight etching of the mask material in a method in accordance with the invention merely results in a slight thinning of the mask, as compared with an increase in window size resulting from a slight etching of side-wall extensions.
There is considerable flexibility in the specific technologies which can be used to form self-aligned structures of the mask together with, for example, an insulating overlayer over the gate in the trench. Such an insulating overlayer permits the source electrode to extend over the trench-gate, which is particularly advantageous in a compact cellular device structure.
Various preferred features in accordance with the invention are set out in claims
2
to
10
.
REFERENCES:
patent: 4767722 (1988-08-01), Blanchard
patent: 4824797 (1989-04-01), Goth
patent: 5082795 (1992-01-01), Temple
patent: 5378655 (1995-01-01), Hutchings et al.
patent: 5972741 (1999-10-01), Kubo et al.
patent: 6087224 (2000-07-01), Luo
patent: 6211018 (2001-04-01), Nam et al.
patent: 6228698 (2001-05-01), Luo
patent: 9403922 (1994-02-01), None
“500-V n-Channel Insulated-Gate Bipolar Transistor with a Trench Gate Structure”, by H.R. Change et al., IEEE Transactions on Electron Devices, Vo. 36, Sep. 1989, No. 9-I.
Hijzen Erwin A.
Maas Henricus G. R.
Timmering Cornelius E.
Elms Richard
Marion Michael E.
Pyonin Adam
U.S. Philips Corporation
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