Manufacture of semiconductor device with salicide electrode

Details Manufacture of semiconductor device with salicide electrode Manufacture of semiconductor device with salicide electrode

1996-08-09

2001-03-06

Quach, T. N. (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S533000, C438S586000, C438S651000, C438S664000, C438S683000

Reexamination Certificate

active

06197646

ABSTRACT:

BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and more particularly to a MOS type semiconductor device with salicide electrodes.
b) Description of the Related Art
As the integration degree of semiconductor integrated circuit devices is becoming high, MOS transistor elements of these devices are scaled down and becoming progressively smaller.
A gate length, for example, has been shortened from sub-micron to half-micron, and has a tendency to further be shortened to 0.35 &mgr;m, 0.25 &mgr;m, and even to 0.1 &mgr;m. The shorter the gate length, the more a high speed operation becomes advantageous. A resistance of a gate electrode is required to be suppressed low even if it is made narrow.
As electrode materials having a low contact resistance to a silicon surface, there are known metal silicides containing Ti, Pt, Co, or other metals. These metal silicides have a low sheet resistance at the interface to silicon, and are suitable for the connection of MOS transistors to wirings such as Al wirings.
Most gate electrodes of MOS transistors use silicon materials such as polycrystalline silicon and amorphous silicon. With a silicon gate electrode, the materials of the source, gate, and drain are all silicon. If a salicide (self-aligned silicide) process is used, contacts can be formed at these silicon regions. In order to make a MOS transistor small, it is necessary to reduce the area of the source/drain regions.
As MOS transistors are becoming small, it is required to form good contacts to small areas of silicon. In addition, as transistors are scaled down, it is necessary not only to shorten gate lengths but also to shallow the source/drain regions in order to avoid a short channel effect.
For example, the depth of source/drain regions is about 150 to 200 nm for a gate length of 0.35 to 0.5 &mgr;m, about 100 nm for a gate length of 0.25 &mgr;m, and about 80 nm for a gate length of 0.15 &mgr;m.
With such small transistors, good contacts are not always formed on silicon by conventional contact forming techniques.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device manufacturing method capable of forming sufficiently good contacts even to small silicon areas.
It is another object of the present invention to provide a semiconductor device manufacturing method including a silicidation process of a Co film excellent in self-alignment.
It is a further object of the present invention to provide a semiconductor device manufacturing method capable of forming a self-aligned low resistance Co silicide film on a fine silicon area defined by a field oxide film.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device including the steps of: forming an insulated gate structure on a p-type active region of a silicon (Si) substrate, the insulated gate structure having side wall insulating regions; implanting arsenic ions in source/drain regions on opposite sides of the insulated gate electrode structure at a dose less than 5×10
15
cm
−2
; forming a laminated layer of a Co film and a TiN film on the surface of the substrate; heating the substrate and reacting the Co film with an underlying Si region for silicidation; and removing the TiN film.
If an As dose is set to 5×10
15
cm
−2
or more, the phenomenon that even if a Co silicide layer is formed, the sheet resistance does not lower sufficiently or the silicide layer is peeled off. By limiting the As dose less than 5×10
15
cm
−2
, silicidation of a Co film formed on the active region advances properly.
If a silicidation reaction of a Co film with underlying Si is performed by heating the substrate while covering the Co film with a TiN film, a low resistance Co silicide electrode can be formed. It is supposed that the TiN film has a protection function.
It is possible to perform a salicide (self-aligned silicide) reaction by forming a laminated film of a Co film and a TiN film on an exposed silicon region defined by an insulating region formed on the surface of a semiconductor substrate.
In the above manner, a semiconductor device with electrodes having a sufficiently low sheet resistance can be formed even if the gate electrode has a short gate length.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including the steps of: forming a field oxide film on the surface of a silicon (Si) substrate for element isolation; implanting ions in the surface region of the Si substrate defined by the field oxide film and forming a conductive silicon region; depositing a Co film on the Si substrate under the condition the Si surface adjacent to the field oxide film is exposed; heating the Si substrate under the conditions of a certain time period and a certain temperature that the Co film reacts with the conductive silicon region for silicidation to form Co silicide, but not to form CoSi
2
; removing an unreacted Co film; and subjecting the Si substrate to another heat treatment and changing the Co silicide to CoSi
2
.
The inventors have found a phenomenon that if a Co film formed on the surface of a silicon substrate including a small active silicon region defined by a field oxide film is silicidated, the silicide film on the small active silicon region creeps up along the field oxide film.
The self alignment property of a salicide film is reduced by such a creep-up phenomenon. If element separation is conducted by a narrow field oxide film, there is a great danger of short-circuit between adjacent elements.
According to the results of experiments made by the inventors, a creep-up of a silicide film along a field oxide film occurs under the conditions where CoSi
2
is formed. This creep-up can be prevented by dividing a cobalt silicide forming process into two steps. At the primary or first heat treatment it is controlled not to form CoSi
2
. Thereafter, the second heat treatment is done to form CoSi
2
after removing an unreacted Co film.
If a silicidation reaction is performed with a Co film covered with a TiN film, it is possible to maintain a good condition of a Co film surface after the silicidation reaction. By performing the first silicidation reaction under the predetermined conditions, a good final silicide film can be formed.
If an unreacted Co film is removed after the first silicidation reaction, there is no Co source so that the advancement of the second silicidation reaction can be controlled. If the unreacted Co film is removed by mixed solution of sulfuric acid and hydrogen peroxide, adverse affects upon the underlying surface can be alleviated. Even if a great quantity of As is doped in the Si surface, there occurs no problem on the surface of the processed substrate. The unreacted Co film may be removed by mixed solution of hydrochloric acid and hydrogen peroxide if a predetermined condition is satisfied.
In the above manner, it is possible to form a low resistance Co silicide film on a fine Si surface defined by a field oxide film. It is therefore possible to manufacture a high performance, high integration semiconductor circuit device.
Other objects, features, and advantages of the invention will become more apparent from the following description taken in connection with the accompanying drawings.


REFERENCES:
patent: 4378628 (1983-04-01), Levinstein et al.
patent: 5047367 (1991-09-01), Wei et al.
patent: 5399506 (1995-03-01), Tsukamoto
patent: 58-46633 (1983-03-01), None
patent: 62-149154 (1987-07-01), None
patent: 62-188223 (1987-08-01), None
Wei, C., et al., “Comparison of Cobalt and Titanium Silicides . . . ”, VMIC Conference, Jun. 12-13, 1989, pp. 241-250.
Berti, C., et al., “A Manufacturable Process for the Formation . . . ”, VMIC Conference, Jun. 9-10, 1992, pp. 267-273.
“0.1 &mgr;m MOS . . . ”, Nikkei Microdevices, Dec. 1993, EDM 93, p. 772.
Yamazaki, T., et al., “21 p Switching 0.1&mgr;m. CMOS . . . ” IEDM 93 Tech. Digest, Dec. 1993, pp. 906-908.
Wang, Q.

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