Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-15
2001-05-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S270000
Reexamination Certificate
active
06228698
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to methods of manufacturing a semiconductor device, for example an insulated-gate field-effect power transistor (commonly termed a “MOSFET”) of the trench-gate type or an insulated-gate bipolar transistor (commonly termed an “IGBT”) of the trench-gate type. The invention also relates to semiconductor devices manufactured by such a method.
Such semiconductor devices are known having source and drain regions of a first conductivity type separated by a channel-accommodating region to which a gate is capacitively coupled, and a localised region of an opposite, second conductivity type which is adjacent to the source region, is contacted by the source electrode and is more highly doped than the channel-accommodating region. A trench-gate device having these features is known from U.S. Pat. No. 5,665,619. The method of manufacture disclosed in U.S. Pat. No. 5,665,619 includes the steps of:
(a) forming at a surface of a semiconductor body a first mask having a first window at a first area of the body where the trench-gate and channel are to be formed,
(b) etching the trench into the body at the first window and providing a gate in the trench where a body region provides the channel-accommodating region,
(c) forming over the gate in the trench a second mask of complementary window pattern to the first mask by providing a differently-etchable material from the first mask in the first window and then etch-removing the first mask from the body while leaving the second mask at the first area where the trench-gate is present, a second area of the body region being present at the complementary window in the second mask,
(d) forming the source region by introducing dopant of the first conductivity type into a part of the second area while masking the trench-gate with the second mask,
(e) forming a localised region of an opposite, second conductivity type by introducing dopant of the second conductivity type into the second area via the second window while masking the trench-gate with the second mask, the localised region being formed to a depth in the body shallower than that of the channel-accommodating region, and
(f) providing a source electrode on the body while masking the trench-gate with the second mask, so as to contact the source region of the first conductivity type and the localised region of the second conductivity type at the surface.
This first mask in U.S. Pat. No. 5,665,619 comprises silicon nitride. The silicon nitride masks underlying areas of the body against oxidation while oxidising an upper part of the gate material to form the second mask of silicon dioxide. This second mask in U.S. Pat. No. 5,665,619 forms a protruding step to the adjacent surface of the body. This step configuration is used in a self-aligned manner to form a further mask with a smaller window, by providing sidewall extensions on the second mask at the step. Thus, U.S. Pat. No. 5,665,619 describes a modified extension of a previously-known trench-gate self-alignment technique, for example as disclosed in U.S. Pat. No. 5,378,655 (our reference PHB 33836). The whole contents of both U.S. Pat. No. 5,378,655 and U.S. Pat. No. 5,665,619 are hereby incorporated herein as reference material. By using such self-aligned techniques as disclosed in U.S. Pat. No. 5,378,655 and U.S. Pat. No. 5,665,619, the number of photolithographic masking steps which require separate alignment can be reduced and compact cellular device structures can be formed.
The localised region of the second conductivity type which is contacted by the source electrode is formed in U.S. Pat. No. 5,665,619 by dopant introduction via the second window, i.e. at a late stage in the manufacturing process. Its localised lateral dimensions are defined by overdoping with a higher dopant concentration of the first conductivity type which is introduced into a part only of the second area in step (d) to form the source region. Thus, the localised region is formed to a shallower depth in the body than both the source region and the channel-accommodating region. However, in terms of improving the blocking/breakdown characteristics of the device, it is advantageous for the localised region to be formed to a greater depth in the body than the channel-accommodating region.
SUMMARY OF THE INVENTION
It is an aim of the present invention to modify the manufacture of trench-gate semiconductor devices and other field-effect semiconductor devices so as to permit the use of self-aligned masking techniques while permitting the localised region to be formed to a greater depth in the body than the channel-accommodating region.
According to the present invention there is provided a method of manufacture wherein the localised region of the second conductivity type is formed by dopant introduction via a first window in a first mask and is thermally diffused to a greater depth in the body than the region accommodating the channel, after which a second mask of complementary window pattern to the first mask is formed by providing a differently-etchable material in the first window and then etch-removing the first mask while leaving the second mask where the localised region is present. The source region is formed by dopant introduction into a second area present at the complementary window in the second mask, i.e. after thermally diffusing the localised region, and the gate is also provided in this second area where the channel-accommodating region is provided.
Thus, the method as set out in claim
1
includes quite different steps (a) to (f) from the method steps of U.S. Pat. No. 5,665,619, and its localised region which is formed via the first window in the first mask can be diffused deep into the body before forming the source region. In this way a deep opposite-conductivity-type region can be obtained to improve the blocking/breakdown characteristics of the device, without adversely affecting the doping profile of the subsequently-formed source region.
Various preferred features in accordance with the invention are set out in claims
2
to
10
.
It is particularly advantageous to use a self-aligned technique within the complementary window of the second mask in order to define the relative extents of the gate, the source region and its contact area. Various options are possible. In one preferred form, sidewall extensions of the second mask may be provided at the second window so as to form a further mask having a smaller window than the second window, and the gate may then be provided at this smaller window.
The gate may advantageously be a trench-gate present in a trench in a major surface, with the channel accomodated adjacent to a sidewall of the trench. The trench may be etched into the body at a/the smaller window to extend through a body region and into an underlying drain region. The dopant forming the source region may, for example, be implanted via the complementary window, or it may, for example, be diffused from doped sidewall extensions provided at the second window.
However, the gate may be a planar-gate which extends over an area of a major surface where the channel is accomodated. In this case, the source region may be formed in step (d) after providing the gate in step (e) so that the gate may form a composite mask pattern with the second mask when introducing the source dopant of the first conductivity type into a part only of the second area. In the case of a trench-gate, it is also possible to form the source region in step (d) after providing the gate in step (e).
REFERENCES:
patent: 5158903 (1992-10-01), Hori et al.
patent: 5322802 (1994-06-01), Baliga et al.
patent: 5324971 (1994-06-01), Notley
patent: 5378655 (1995-01-01), Hutchings et al.
patent: 5633181 (1997-05-01), Hayashi
patent: 5665619 (1997-09-01), Kwan et al.
patent: 5864167 (1999-01-01), Cutter
Biren Steven R.
Dang Phuc T.
Nelms David
U.S. Philips Corporation
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