Manufacture of a semiconductor device with retrograded wells

Details Manufacture of a semiconductor device with retrograded wells Manufacture of a semiconductor device with retrograded wells

1999-03-26

2002-07-02

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S200000, C438S232000, C438S275000, C438S279000

Reexamination Certificate

active

06413814

ABSTRACT:

BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device with dynamic random access memories (DRAMs) and its manufacture method.
b) Description of the Related Art
DRAMs are widely used as storage devices. The application fields of DRAMs are expanding to portable electronic apparatuses, and there is a great need for low power consumption of DRAMs. The capacity of a battery housed in a portable electronic apparatus is limited so that the less the storage device consumes power, the better.
It is necessary for a DRAM to rewrite its data at a predetermined time interval. The memory cell of a DRAM generally has one transistor and one capacitor. Electric charges stored in the capacitor indicate the contents of stored data. One electrode of the capacitor is connected to one electrode (storage node) of the transistor, and the stored charges gradually reduce because of leak current from the storage node.
In order to recover the reduced, stored charges, the data is required to be rewritten. This data rewrite operation is called a refresh operation. If the refresh period is short, the power consumption becomes large. In order to reduce this power consumption, it is efficient to prolong the period of the refresh operation. To this end, it is desired to improve the data retention characteristics (refresh characteristics) of a storage node.
The refresh characteristics are deteriorated by junction leak current flowing out of a diffusion layer which forms part of the storage node of the memory cell, and dominantly affected by defects caused by contamination during the manufacture processes or other reasons. There are many presumable reasons but they are not still definitely decided to be actual reasons.
According to a report of IEDM95 (1995), pp. 915-918, a retention (holding) time of DRAM is largely dependent upon the impurity concentration of a well in which the DRAM cell is formed, and the higher the well impurity concentration, the worse the refresh characteristics. This report analyzes that as the well concentration is raised, thermal ion field emission (TFE) current increases and forms a tail distribution of the retention time.
Techniques of forming DRAMs by using a retrograde triple well has been proposed (for example, U.S. Pat. No. 5,404,042 and JP-A 8-97378, which are incorporated herein by reference). The triple well is a combination of a double well, and complementary single or simple wells. The double well of the triple well structure is also called a triple well, implying that it is accompanied with a simple well of the same conductivity type. A retrograde well is a well having a maximum impurity concentration at a deep position in the well.
If a memory cell is implemented in a retrograde well formed as the inner well of the double well constituting the triple well, the memory cell becomes very resistant to a-ray soft errors. The manufacture process of a retrograde well, using high energy ion implantation, is simple and manufacture cost can be lowered. In addition, resistance to latch-up is excellent in a retrograde well.
FIGS. 10A-10E
are cross sectional views illustrating a conventional method of manufacturing DRAMs using the retrograde well.
As shown in
FIG. 10A
, the surface of a p-type silicon substrate
101
is oxidized to grow a silicon oxide film (buffer film)
130
to a thickness of 3 nm. A silicon nitride film
131
is deposited 115 nm thick on the silicon oxide film
130
by CVD. The silicon nitride film
131
is patterned through photolithography using a resist mask.
Thereafter, a photoresist mask
123
b
is formed which has openings in the areas corresponding to n-type wells to be next formed. Phosphorous ions are implanted at an acceleration energy of 180 keV and at a dose of 1.4×10
13
cm
−2
to form n-type regions
102
a
and
102
b.
After the photoresist mask
123
b
is removed, the substrate is subjected to heat treatment for 90 minutes at 1150° C. to form deep n-type wells
102
a
and
102
b.
As shown in
FIG. 10B
, by using the patterned silicon nitride film
131
as a mask, wet oxidation is performed at 1100° C. to selectively grow field oxide films
125
of 350 nm thickness on the silicon substrate. Thereafter, the silicon nitride film
131
and silicon oxide buffer film
130
are removed. Dry oxidation is performed at 900° C. to grow silicon oxide films (not shown) of 10 nm thickness in the areas where the field oxide films
125
are not formed.
As shown in
FIG. 10C
, a photoresist mask
123
c
is formed. This photoresist mask
123
c
has openings which expose a partial area of the exposed surface of the p-type silicon substrate
101
and a partial area of the n-type well
102
b.
Boron ions are implanted to form p-type regions
104
and
103
. Ion implantation is performed three times, at an acceleration energy of 180 keV and a dose of 1.5×10
13
cm
−2
, at an acceleration energy of 100 keV and a dose of 2×10
12
cm
−2
, and at an acceleration energy of 50 keV and a dose of 1×10
12
cm
−2
, respectively.
The ion implantation at the acceleration energy of 180 keV forms a retrograde portion having a high impurity concentration at a bottom portion of the well. The next ion implantation at the acceleration energy of 100 keV sets the threshold value Vt of a parasitic field transistor under the field oxide film
125
higher than a certain value to form a so-called channel stop region. The ion implantation at the acceleration energy of 50 keV interconnects a p-type region finally formed by ion implantation for adjusting a threshold value of n-channel MOS transistors to be formed later and the p-type region formed at the acceleration energy of 100 keV.
Thereafter, the photoresist mask
123
c
is removed. After the photoresist mask
123
c
is removed, boron ions are implanted over the whole surface of the substrate at an acceleration energy of 18 keV and a dose of 2×10
12
cm
−2
. This ion implantation sets desired threshold values of p-channel MOS transistors to be formed in the n-type wells
102
a
and
102
b
and n-channel MOS transistors to be formed in the p-type well
104
and in a peripheral circuit region
103
a
in the p-type triple well
103
.
As shown in
FIG. 10D
, a photoresist mask
123
d
is formed over the semiconductor substrate surface. This photoresist mask
123
d
has an opening which exposes a memory cell region
103
b
of the p-type triple well
103
. By using the photoresist mask
123
d
as a mask, boron ions are implanted at an acceleration energy of 18 keV and a dose of 3×10
12
cm
−2
. This ion implantation sets the threshold value Vt of a transfer transistor to be formed in the memory cell region
103
b
higher than that of a transistor to be formed in the peripheral circuit region
103
a.
Thereafter, the photoresist mask
123
d
is removed.
After the photoresist mask
123
d
is removed, the oxide film of 10 nm thickness formed before the ion implantation processes is removed, and the semiconductor substrate is processed in a dry oxidizing atmosphere at 900° C. to grow a gate oxide film of 10 nm thickness.
FIG. 10E
is a schematic diagram showing the triple well structure formed as above. The n-type well
102
a
and p-type well
104
are used for forming p-channel MOS transistors and n-channel MOS transistors of a peripheral circuit.
The exposed region of the n-type well
102
b
and the p-type well region
103
a
in the n-type well
102
b
are used for forming a CMOS sense amplifier circuit. The p-type well region
103
b
in the n-type well
102
b
is used for forming memory cells.
With the ion implantation processes described above, the threshold values of MOS transistors to be formed in respective regions can be regulated or adjusted to desired values. Thereafter, an insulated gate electrode (word line), a source/drain region (bit line), a capacitor, and the like are formed by usual manufacture processes.
The above-described manufact

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