Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-10-11
2005-10-11
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000, C711S145000, C365S049130
Reexamination Certificate
active
06954828
ABSTRACT:
The present invention relates to the management of caches in a data processing apparatus, and in particular to the management of caches of the type where data in the cache may be designated as locked to prevent that data from being overwritten. The data processing apparatus comprises a processor, an n-way set associative cache having a plurality of entries, each entry being arranged to store one or more data values and a corresponding address identifier, the processor being operable to select one or more of the n-ways to operate in a lockdown mode, the lockdown mode being used to lock data values into the corresponding way, and a plurality of lockdown controllers. Each lockdown controller is associated with a corresponding way and comprises an address register arranged to store an address range specified by the processor such that, when the corresponding way is in the lockdown mode, only data values whose address identifiers are within the address range are locked into the corresponding way. This technique provides for reduced complexity during lockdown because in preferred embodiments a dedicated lockdown program is not required to carefully manage the storage of data values in the lockdown, the lockdown occurs automatically.
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ARM Limited
Chace Christain P.
Nixon & Vanderhye P.C.
Sparks Donald
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