Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
2007-04-03
2007-04-03
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S500000, C713S600000
Reexamination Certificate
active
10329378
ABSTRACT:
Maintaining synchronization when sending/receiving multiple channels of data with a corresponding common reference clock signal. Synchronization signals (e.g., pulses) are generated periodically and the timing of channels is adjusted. In an embodiment, multiple sequences of parallel data elements are received on corresponding parallel data channels using a first common clock signal. Each sequence of parallel data elements is converted to a corresponding sequence of serial data elements. The serial data elements are transmitted on a corresponding serial channel using a serial clock as a common reference. A synchronization signal may be generated periodically with a time period of (the number of bits in each parallel data element x the time period of the serial clock), wherein ‘x’ represents multiplication operation. As the parallel data channels are synchronized in short intervals, synchronization is maintained.
REFERENCES:
patent: 5796794 (1998-08-01), Kim
patent: 6658582 (2003-12-01), Han
patent: 2004/0004564 (2004-01-01), Hattori
patent: 2004/0051655 (2004-03-01), Seo et al.
Brady W. James
Brown Michael J.
Marshall, Jr. Robert D.
Perveen Rehana
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