Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-08-08
2004-08-17
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S287000, C438S289000, C438S303000
Reexamination Certificate
active
06777281
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating MOS transistors with LDD regions, wherein the series resistance of the LDD regions is maintained by retarding dopant segregation into an overlying liner oxide layer, and to MOS transistors obtained thereby. The method has particular utility in the manufacture of high speed integrated circuit (IC) semiconductor devices.
BACKGROUND OF THE INVENTION
The escalating requirements for high integration density and performance associated with ultra-large scale (“ULSI”) integration semiconductor devices are difficult to satisfy in terms of achieving pre-selected, or desired, device characteristics, including, inter alia, drive currents and series resistance of LDD portions of source and drain regions of MOS transistors. As a consequence of such difficulty in achieving desired device characteristics, significant device rejection rates may be experienced in large-scale manufacture, leading to increased cost.
According to methodology currently employed in the manufacture of MOS transistors, a thin gate oxide layer and an overlying gate electrode layer, typically a polysilicon layer, are formed over the surface of a semiconductor substrate, followed by selective removal processing, as by anisotropic etching, to define a gate electrode/gate oxide layer stack overlying a portion of the substrate surface. LDD regions which extend for a short distance beneath the side edges of the gate electrode/gate oxide layer stack are then formed to a shallow depth in portions of the substrate not covered by the gate electrode/gate oxide layer stack, typically by implantation of dopant-containing ions, utilizing the gate electrode/gate oxide layer stack as an implantation mask. A thin liner oxide layer is then formed over the exposed portions of the substrate surface, i.e., the just-formed LDD regions, and over the side edge and top surfaces of the gate electrode/gate oxide layer stack. Insulative sidewall spacers are then formed on the portions of the thin liner oxide layer covering the side edge surfaces of the gate electrode/gate oxide layer stack and adjacent portions of the substrate surface, as by depositing a blanket layer of an electrically insulative material, e.g., a silicon oxide or nitride, over each of the exposed surfaces, followed by selectively anisotropically etching the blanket layer. More heavily-doped source and drain regions are then formed in the respective LDD regions at a deeper level below the substrate surface, as by implantation of dopant-containing ions, utilizing the gate electrode/gate oxide layer stack with sidewall spacers thereon as an implantation mask. A thermal annealing process is then performed in order to activate the implanted dopant species and effect source/drain junction formation.
A drawback associated with the above-described conventional process scheme for MOS transistor formation is the tendency for the dopant species to upwardly move from LDD regions in silicon (Si) and segregate in the overlying thin liner oxide layer, thereby resulting in dopant concentrations in the LDD regions which are less than desired or optimal. As a consequence, the series resistance of the LDD regions is greater than the design value therefor, and the device drive current is disadvantageously decreased. The effect of dopant movement from the LDD regions upwardly into the overlying thin liner oxide layer is especially significant when p-doped LDD regions are formed by implantation of boron (B) ions or indium (In) ions.
In view of the foregoing, there exists a need for methodology enabling the formation of microelectronic devices, e.g., MOS transistors and MOS transistor-based devices, such as CMOS devices, which enables a substantial and significant reduction in the tendency for dopant segregation in thin liner oxide layers overlying LDD regions, whereby disadvantageous increase in the series resistance of the LDD regions and decreased drive currents of the MOS transistors are effectively prevented, or at least minimized.
The present invention, wherein a species which effectively retards movement of dopant species from LDD regions into overlying, thin liner oxide layers, is incorporated in the thin liner oxide layers, effectively addresses and solves the problems of increased series resistance and decreased device drive current associated with the conventional MOS transistor fabrication methodology, while maintaining full compatibility with all other aspects of conventional technology for automated manufacture of microelectronic devices such as IC devices. Further, the methodology afforded by the present invention can be readily and easily implemented in cost-effective manner utilizing conventional deposition/implantation techniques. Finally, the methodology of the present invention enjoys diverse utility in the manufacture of numerous and various types of semiconductor devices and/or components.
DISCLOSURE OF THE INVENTION
An advantage of the present invention is an improved method of manufacturing a semiconductor device.
Another advantage of the present invention is an improved method of manufacturing a MOS transistor device.
Still another advantage of the present invention is an improved method of manufacturing a MOS transistor device comprising boron (B)-doped or indium (In)-doped LDD regions.
A still further advantage of the present invention is an improved semiconductor device.
A yet another advantage of the present invention is an improved MOS transistor device.
An additional advantage of the present invention is an improved MOS device comprising boron (B)-doped or indium (In)-doped LDD regions.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the present invention may be realized as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are obtained in part by a method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate including at least one dopant species-containing region extending to a surface of the substrate;
(b) forming a thin liner oxide layer on the surface of the substrate; and
(c) incorporating in the thin line oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.
According to alternative embodiments of the present invention, steps (b) and (c) are performed simultaneously, or steps (b) and (c) are performed sequentially in the recited order.
In accordance with certain embodiments of the present invention, step (a) comprises providing a silicon (Si)-based semiconductor substrate including at least one p-type or n-type dopant species-containing region extending to a surface of said substrate; step (b) comprises forming a thin liner oxide layer comprised of a silicon oxide; and step (c) comprises implanting the thin liner oxide layer with ions of at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.
According to particular embodiments of the present invention, step (a) comprises providing a Si-based semiconductor substrate including at least one boron (B)-doped or indium (In)-doped p-type region extending to a surface of the substrate; and step (c) comprises implanting at least one of nitrogen (N)-containing and germanium (Ge)-containing ions in the thin liner oxide layer.
In accordance with preferred embodiments of the present invention, step (a) comprises providing a semiconductor substrate including:
(i) a thin gate insulator layer in overlying contact with a portion of the substrate surface;
(ii) an electrically
Kadosh Daniel
Luning Scott D.
Sultan Akif
Wu David
Advanced Micro Devices , Inc.
Lindsay Jr. Walter L.
Niebling John F.
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