Main row decoder in a semiconductor memory device

Details Main row decoder in a semiconductor memory device Main row decoder in a semiconductor memory device

2005-12-06

2005-12-06

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189080, C365S222000, C365S230080

Reexamination Certificate

active

06973007

ABSTRACT:
The disclosure is a main row decoder of a semiconductor memory device including: a bank controller for generating an internal RAS signal in response to an active and precharge signal; a first pulse generator for generating a first pulse signal when the internal RAS signal transitions; a second pulse generator for generating a second pulse signal when the internal RAS signal or a self refresh signal transitions; an address latch circuit for latching the least significant bit of a row address in response to the first pulse signal; and a row pre-decoder for decoding outputs of the address latch circuit in response to the second pulse signal.

REFERENCES:
patent: 5940342 (1999-08-01), Yamazaki et al.
patent: 6212126 (2001-04-01), Sakamoto
patent: 6373783 (2002-04-01), Tomita
patent: 6507526 (2003-01-01), Ohtake
patent: 6674684 (2004-01-01), Shen

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