Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2003-01-10
2004-12-07
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S171000, C365S173000
Reexamination Certificate
active
06829161
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to magnetic memory systems, and more particularly to a method and system for providing an element that employs a spin transfer effect in switching and that can be used in a magnetic memory such as magnetic random access memory (“MRAM”).
BACKGROUND OF THE INVENTION
Magnetic memories are often used in storing data. One type of memory element currently of interest utilizes magnetoresistance of a magnetic element for storing data
FIGS. 1A and 1B
depict conventional magnetic elements
1
and
1
′. The conventional magnetic element
1
is a spin valve
1
and includes a conventional antiferromagnetic layer
2
, a conventional pinned layer
4
, a conventional spacer layer
6
and a conventional free layer
8
. The conventional pinned layer
4
and the conventional free layer
8
are ferromagnetic. The conventional spacer layer
6
is norunagnetic. The conventional spacer layer
6
is conductive. The antiferromagnetic layer
2
is used to fix, or pin, the magnetization of the pinned layer
4
in a particular direction. The magnetization of the free layer
8
is free to rotate, typically in response to an external magnetic field.
The conventional magnetic element
1
′ is a spin tunneling junction. Portions of the conventional spin tunneling junction
1
′ are analogous to the conventional spin valve
1
. Thus, the conventional magnetic element
1
′ includes an antiferromagnetic layer
2
′, a conventional pinned layer
4
′, an insulating barrier layer
6
′ and a free layer
8
′. The conventional barrier layer
6
′ is thin enough for electrons to tunnel through in a conventional spin tunneling junction
1
′.
Depending upon the orientations of the magnetizations of the free layer
8
or
8
′ and the pinned layer
4
or
4
′, respectively, the resistance of the conventional magnetic element
1
or
1
′, respectively, changes. When the magnetizations of the free layer
8
and pinned layer
4
are parallel, the resistance of the conventional spin valve
1
is low. When the magnetizations of the free layer
8
and the pinned layer
4
are antiparallel, the resistance of the conventional spin valve
1
is high. Similarly, when the magnetizations of the free layer
8
′ and pinned layer
4
′ are parallel, the resistance of the conventional spin tunneling junction
1
′ is low. When the magnetizations of the free layer
8
′ and pinned layer
4
′ are antiparallel, the resistance of the conventional spin tunneling junction
1
′ is high.
In order to sense the resistance of the conventional magnetic element
1
/
1
′, current is driven through the conventional magnetic element
1
/
1
′. Current can be driven through the conventional magnetic element
1
in one of two configurations, current in plane (“CIP”) and current perpendicular to the plane (“CPP”). However, for the conventional spin tunneling junction
1
′, current is driven in the CPP configuration. In the CIP configuration, current is driven parallel to the layers of the conventional spin valve
1
. Thus, in the CIP configuration, current is driven from left to right or right to left as seen in FIG.
1
A. In the CPP configuration, current is driven perpendicular to the layers of conventional magnetic element
1
/
1
′. Thus, in the CPP configuration, current is driven up or down as seen in
FIG. 1A
or
1
B. The CPP configuration is used in MRAM having a conventional spin tunneling junction
1
′ in a memory cell.
FIG. 2
depicts a conventional memory array
10
using conventional memory cells
20
. Each conventional memory cell
20
includes a conventional magnetic element
1
/
1
′, depicted as a resistor in FIG.
2
. The conventional memory array
10
typically uses a spin tunneling junction
1
′. The conventional array
10
is shown as including four conventional memory cells
20
. Each memory cell
20
includes a conventional spin tunneling junction
1
′ and a transistor
22
. The memory cells
20
are coupled to reading/writing column selection
30
via bit lines
32
and
34
and to row selection
50
via word lines
52
and
54
. Also depicted are write lines
60
and
62
which carry currents that generate external magnetic fields for the corresponding conventional memory cells
20
during writing. The reading/writing column selection
30
is coupled to write current source
42
and read current source
40
which are coupled to a voltage supply Vdd
48
via line
46
.
In order to write to the conventional memory array
10
, the write current Iw
42
is applied to the bit line
32
or
34
selected by the reading/writing column selection
30
. The read current Ir
40
is not applied. Both word lines
52
and
54
are disabled. The transistors
22
in all memory cells are disabled. In addition, one of the write lines
60
and
62
selected carries a current used to write to the selected conventional memory cell
20
. The combination of the current in the write line
60
or
62
and the current in the bit line
32
or
34
generates a magnetic field large enough to switch the direction of magnetization of the free layer
8
′ and thus write to the desired conventional memory cell
20
. Depending upon the data written to the conventional memory cell
20
, the conventional magnetic tunneling junction
1
′ will have a high resistance or a low resistance.
When reading from a conventional cell
20
in the conventional memory array
10
, the read current Ir
40
is applied instead. The memory cell
20
selected to be read is determined by the row selection
50
and column selection
30
. The output voltage is read at the output line
44
.
Although the conventional magnetic memory
10
using the conventional spin tunneling junction
1
′ can function, one of ordinary skill in the art will readily recognize that there are barriers to the use of the conventional magnetic element
1
′ and the conventional magnetic memory
10
at higher memory cell densities. In particular, the conventional memory array
10
is written using an external magnetic field generated by currents driven through the bit line
32
or
34
and the write line
60
or
62
. In other words, the magnetization of the free layer
8
′ is switched by the external magnetic field generated by current driven through the bit line
32
or
34
and the write line
60
or
62
. The magnetic field required to switch the magnetization of the free layer
8
′, known as the switching field, is inversely proportional to the width of the conventional magnetic element
1
′. As a result, the switching field increases for conventional memories having smaller magnetic elements
1
′. Because the switching field is higher, the current required to be driven through the bit line
32
or
34
and particularly through the write line
60
or
62
increases dramatically for higher magnetic memory cell density. This large current can cause a host of problems in the conventional magnetic memory
10
. For example, cross talk and power consumption would increase. In addition, the driving circuits required to drive the current that generates the switching field at the desired memory cell
20
would also increase in area and complexity. Furthermore, the conventional write currents have to be large enough to switch a magnetic memory cell but not so large that the neighboring cells are inadvertently switched. This upper limit on the write current amplitude can lead to reliability issues because the cells that are harder to switch than others (due to fabrication and material nonuniformity) will fail to write consistently.
Accordingly, what is needed is a system and method for providing a magnetic memory element which can be used in a memory array of high density, low power consumption, low cross talk, and high reliability, while providing sufficient read signal. The present invention addresses the need for such a magnetic memory element.
SUMMARY OF THE INVENTION
Albert Frank
Huai Yiming
Nguyen Paul P.
Grandis Inc.
Hoang Huan
Sawyer Law Group LLP
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