Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-30
2004-04-06
Ho, Hoai (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S421000, C365S173000, C365S158000
Reexamination Certificate
active
06717194
ABSTRACT:
BACKGROUND
The present invention relates to magneto-resistive memories, and more particularly to magneto-resistive bit structures and method of manufacture therefor.
Magneto-resistive memories are non-volatile. That is, the data stored in the memory are maintained even if power is lost or otherwise interrupted. Typical magneto-resistive memories use variations in the magnetization direction of a thin film of ferromagnetic material to represent and to store a binary state. Each thin film of ferromagnetic material can be referred to as a magneto-resistive bit. During a write operation, the magnetization direction of a selected bit structure is set by passing an appropriate current near the selected bit structure, often using a word line and/or digital line and/or sense current. The current produces a magnetic field that sets the magnetization direction of at least one of the layers in the ferromagnetic film in a desired direction. The magnetization directions dictate the magneto-resistance of the film. During a subsequent read operation, the magneto-resistance of the film can be read by passing a sense current through the bit structure via a sense line or the like.
Some prior art magneto-resistive bit structures are shown and described in U.S. Pat. No. 4,731,757 to Daughton et al. and U.S. Pat. No. 4,780,848 to Daughton et al., both of which are assigned to the assignee of the present invention and both of which are incorporated herein by reference. Illustrative processes for forming such magnetic bit structures are shown and described in U.S. Pat. No. 5,569,617 to Yeh et al. and U.S. Pat. No. 5,496,759 to Yue et al., both of which are assigned to the assignee of the present invention, and both of which are incorporated herein by reference.
Such magneto-resistive memories are often conveniently provided on the surface of a monolithic integrated circuit to provide easy electrical interconnection between the bit structures and the memory operating circuitry on the monolithic integrated circuit. To provide a sense current through the bit structure, for example, the ends of the bit structure are typically connected to adjacent bit structures through a metal interconnect layer. The string of bit structures then forms a sense line, which is often controlled by operating circuitry located elsewhere on the monolithic integrated circuit.
For many magneto-resistive memories, it is desirable to reduce the size of the ferromagnetic thin film bit structures to achieve significant density of stored digital bits. Because of the desire to reduce the size of the bit structures, the width of the bit structures is often smaller than the minimum allowed width of the contact and/or vias that are used to form the connection to the bit structure. As a result, the contact or via holes typically overlap the lateral edges of the bit structure as shown in, for example, U.S. Pat. No. 4,731,757 to Daughton et al. and U.S. Pat. No. 4,780,848 to Daughton et al.
A limitation of such an approach is that conventional integrated circuit processes often cannot be used to form the contact and/or via holes to the bit structure. For example, in a conventional integrated circuit process, the contact and via holes are often formed by first providing a patterned photoresist layer over the integrated circuit. The patterned photoresist layer defines the location and size of the contact and/or via holes that are used to make contact to the bit structure. Once the photoresist layer is in place, an etching process is used to etch the contact or via holes down to the bit structure. As indicated above, however, the contact and/or via holes often overlap the edge of a bit structure. In some conventional etching processes, the solvents used to perform the etch may damage the edges of the bit structure.
Once the contact or via holes are etched, a conventional oxygen asher photoresist removal step would typically be used to remove the photoresist layer. However, because the contact and/or via holes overlap the edge of the bit structure, the oxygen asher photoresist removal step may oxidize the sidewalls of the ferromagnetic bit structure, and can significantly damage the edges of the bit structure.
Because of the potential damage to the bit structure, many magnetic memory processes do not use conventional etch and photoresist removal steps when forming the contacts and/or via holes to the magnetic bit structures. Instead, specialized process techniques are often incorporated into the manufacturing process. For example, and continuing with the above example, the oxygen asher photoresist removal step may be replaced with other process steps that are less likely to oxidize the side wall of the magnetic film material, such as using a “wet” photoresist removal strip. Other techniques may also be used include providing spacers adjacent the exposed edges of the bit structure in an attempt to protect the edges from subsequent process steps. While these specialized techniques may reduce the risk of oxidization of the bit edges, such processes often cause higher defect densities than conventional photoresist steps, and may have other negative effects on the operation of the magneto-resistive bit structures.
What would be desirable, therefore, is a magneto-resistive bit structure that does not require special processing steps when forming the contacts or via holes to the bit structure. More specifically, what would be desirable is a magneto-resistive bit structure that can be formed without directly exposing the bit edges of the bit structure to the etch and/or removal steps. This may allow more efficient and reliable back-end processing, which in turn, may reduce the defect density and increase the yield of the devices.
SUMMARY
The present invention overcomes many of the disadvantages of the prior art by providing a magnetic bit structure that can be produced using conventional contact and or via processing steps. This is preferably accomplished by providing a magnetic bit structure that has bit ends that are sufficiently large to accommodate a minimum size contact or via hole. As such, the contact or via holes may remain inside of the bit edges, thereby protecting the edges of the bit from later process steps that would otherwise cause oxidation or damage the bit structure.
In one illustrative embodiment, the magneto-resistive bit of the present invention includes a first bit end with a first contact structure. The first bit end is preferably dimensioned to extend laterally around the perimeter of the first contact structure. This arrangement may allow the first contact structure to contact only the top surface of the magneto-resistive bit, while protecting the side walls of the bit. The magneto-resistive bit may also include a second bit end with a corresponding second contact structure. Like the first bit end, the second bit end is preferably dimensioned to extend laterally around the perimeter of the second contact structure.
To retain many of the magnetic properties of a narrow magneto-resistive bit, it is contemplated that the magneto-resistive bit may include an elongate central section having a width that is narrower than the width of the first and second bit ends. In this configuration, the data is preferably stored in the elongated central section, rather than in the first or second bit ends. Several performance advantages result. First, one and/or both bit ends are not subjected to current flow between the two contacts. By not subjecting the bit ends to fields from currents from the contacts, undesired switching of the bit ends is reduced. Second, because the current path for the bit is restricted to the region between the contacts, current does not flow near the bit ends. The net result is to reduce electrical bit resistance and to increase the figure-of-ment of the ratio of the magneto-resistive change-in-resistance to the bit resistance.
In an illustrative method of the present invention, the magneto-resistive bit is preferably formed on a relatively planar surface of an integrated circuit. The magneto-resistive bit is then f
Arrott Anthony
Berg Lonny
Katti Romney R.
Larson William
Li Shaoping
Ho Hoai
Knobbe Martens Olson & Bear LLP
Tran Long
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