Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-09-13
2004-04-13
Vinh, Lan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S055000, C438S064000, C438S108000, C438S708000, C438S712000, C438S718000, C216S058000, C216S066000
Reexamination Certificate
active
06720270
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to schemes of reducing the size of at least a semiconductor unit, particularly to technologies of reducing the size of at least a semiconductor unit in packaging the semiconductor unit.
BACKGROUND OF THE INVENTION
In conventional processes of packaging an IC chip, back-side grinding of a wafer is the first step which is followed by wafer sawing to divide a wafer into a plurality of dice, and the dice are then attached to substrates. According to such conventional processes, grinding on the basis of mechanical force is still applied to a chip even when the thickness of the chip approximates an expected specification, resulting in the fact that the chip tends to suffer from back-side chipping. This result is particularly serious in case the expected specification of the thickness of the chip is relatively small. Furthermore, a chip so ground as to have a critical thickness (such as 6 mil or below) tends to suffer from die crack, and the process of back-side grinding of a chip, particularly when the thickness of the chip approximates the expected specification, always involves petty but indispensable procedures. It can thus be concluded that the cost optimization for such conventional IC packaging processes and the quality stabilization of product therein can never be realized due to the need thereof for complicated and petty procedures, and the significant failure rate inherent therein resulting from back-side chipping and die crack.
To provide solutions to the above problems which are associated with conventional chip packaging processes, the present invention develops new schemes for reducing the size of a chip, which features replacing conventional back-grinding of a chip by the etching on a surface of the chip, particularly during the phase the thickness of the chip reaches a range of 8~10 mil, thereby the failure rate of process of packaging at least a chip can be significantly lowered, and the petty procedures involved by grinding a thin chip can be abridged.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for reducing the size of a semiconductor unit, in order to immunize semiconductor unit packaging processes against the back-side chipping resulting from back-side grinding of a thin chip, and the die crack resulting from sawing a wafer, or handling, or processing, or connecting a chip.
Another object of the present invention is provide a method for reducing the size of a semiconductor unit, in order to eliminate the need of petty procedures in grinding a thin wafer.
A further object of the present invention is to provide different etching modes for industries to select, according to individual product or condition, better scheme for reducing the size of at least a semiconductor unit in the processes of packaging at least a semiconductor unit, thereby the cost of an IC package can be economized, and the stable product quality thereof can be reliably sustained.
The primary difference between the present invention and those conventional arts of packaging a chip is briefed as follows: according to those conventional arts, the size of a chip/die is reduced by grinding on the basis of mechanical force throughout the whole process of packaging a chip/die; while according to the present invention, the size of at least a semiconductor unit is reduced by etching the semiconductor unit, particularly when the thickness of the semiconductor unit approximates an expected specification (such as the thickness in the range spanning between 8 mil and 10 mil).
The present invention is characterized by using a certain type of gas (plasma, for example) or beams of light to etch at least a thin semiconductor unit until the size of the semiconductor unit meets an expected specification (such as the thickness thereof ranging from 2 mil to 6 mil), thereby IC packaging processes can be immunized against the high failure rate resulting from back-side chipping of a thin chip and die crack.
An aspect of the present invention for reducing the size of at least a semiconductor unit in a process of packaging the semiconductor unit may be a method comprising the steps of:
(A) attaching at least a part of a first surface of the semiconductor unit to a carrier such as a chip carrier (a substrate, for example) or a chip tray; and
(B) etching the semiconductor unit from a second surface of the semiconductor unit until the size of the semiconductor unit meets an expected specification.
In the process of reducing the size of semiconductor unit according to the above method, the semiconductor unit has its semiconductor electrical connection device such as a pin located on its first surface, and the semiconductor unit may be etched by means selected from among using gas and using beams of light. A preferred embodiment is to etch the semiconductor unit by using plasma.
In the process of reducing the size of semiconductor unit according to the above method, the expected specification may mean that the thickness of the semiconductor unit measured relative to the first surface is within a specified range, and the specified range may be a range spanning between 2 mil and 6 mil, for example. If the initial thickness of the semiconductor unit is too much larger than the specified range, back-side grinding of the semiconductor unit may be used to reduce the size of the semiconductor unit until the thickness of the semiconductor unit approximates the specified range, such as the range spanning between 8 mil and 10 mil. In the range spanning between 8 mil and 10 mil, grinding on the basis of mechanical force tends to result in high failure rate, and therefore is replaced by the etching process characterizing the present invention.
The above method is suitable for packaging at least a semiconductor unit that, after attaching to the chip carrier, has at least a surface from which the semiconductor unit may be etched. For example, a flip chip with a surface thereof connected with the chip carrier via bumps may have another surface from which the flip chip may be etched, or in a lead-on chip package a chip having part of its first surface stuck to the chip carrier and its bonding wires electrically connected to the chip carrier may have its second surface for etching the chip. The meaning of “attaching” throughout this disclosure includes “placing”, and the semiconductor unit may also be properly placed onto a chip tray instead of a chip carrier.
Another aspect of the present invention for reducing the size of at least a semiconductor unit in a process of packaging the semiconductor unit which includes a first surface, a second surface, and at least a semiconductor electrical connection device located on the first surface, may be a method comprising the steps of:
(C) attaching the semiconductor unit to a seating apparatus such as a chip tray, or a chip carrier mechanically or/and electrically connectible with said semiconductor unit, the fast surface thereof facing the seating apparatus and the second surface thereof exposed; and
(D) etching the semiconductor unit from its second surface until the size of the semiconductor unit meets an expected specification, thereby the method provided by the present invention can be suitable for various IC package structures, as can be seen from detailed descriptions hereinafter.
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Siliconware Precision Industries Co. Ltd.
Vinh Lan
LandOfFree
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