Magnetically enhanced plasma oxide etch using...

Details Magnetically enhanced plasma oxide etch using... Magnetically enhanced plasma oxide etch using...

2002-05-13

2003-09-02

Hiteshaw, Felisa (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S706000, C438S710000, C438S711000, C438S723000

Reexamination Certificate

active

06613689

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to plasma etching. In particular, the invention relates to a method of etching oxide layers in semiconductor integrated circuits with a magnetically enhanced plasma etch reactor.
BACKGROUND ART
Modem silicon integrated circuits contain millions to tens of millions of interconnected semiconductor devices. Such a high level of integration has been achieved, at least in part, by decreasing the minimum feature sizes and by providing multiple wiring layers of horizontally extending metallization lines. Dielectric layers separate the wiring layers, which are selectively connected with small-area vertical metallization interconnects. In the case of a dielectric layer separating two metallization layers, the vertical interconnect is called a via when it makes the connection between these metallization layers. However, the vertical interconnect is called a contact hole when it connects the first metallization layer to the semiconductor devices built on the silicon substrate. This invention will be primarily described with respect to the formation of the via or contact holes by dry plasma etching. After such holes are etched, they are filled with a metallization, such as tungsten, thereby forming the vertical connection.
As will be explained below, etching of the via or contact holes is presenting increasing difficulty in advanced structures because of their decreasing widths and increasing aspect ratios. Since this invention is applicable to both via and contact etches (and other dielectric etch applications), the terms “via” and “contact” may be used nearly interchangeably in the following text hereafter without distinguishing specialized portions of the process specific to one or the other.
The inter-level dielectric has conventionally been composed of a silica-based oxide, whether it is silicon dioxide grown in a plasma CVD process using TEOS, or a borophosphate silicate glass (BPSG) deposited as a spin on glass, or other dielectric materials. More recently, low-k dielectric materials have been developed for use as inter-level dielectrics. Their lower dielectric constants offer the possibility of reduced capacitive coupling between horizontally or vertically adjacent lines, thus reducing cross talk, power consumption, and signal rise time. Low-k dielectrics have been proposed having varying compositions, some silicon-based, and other carbon-based.
A typical advanced via hole is illustrated in the cross-sectional view of
FIG. 1. A
lower dielectric layer
10
includes a metal feature
12
, such as a metallization line for the underlying layer
10
. An upper dielectric layer
14
is deposited on the lower dielectric layer
10
and the metal feature
12
. A step of chemical mechanical polishing (CMP) may be used to planarize the top surface of the dielectric layer
14
. A photoresist layer
16
is spun onto the upper dielectric layer
14
and dried, and photographic means are used to expose and develop a photomask aperture in the area overlying the metal feature
12
in which the via is to be formed. The original upper profile of the patterned photoresist prior to etching is shown by line
16
′. A plasma etching step uses the patterned photoresist layer as a photomask to etch through the dielectric layer
14
to the underlying metal feature
12
to form a via hole
20
. The step of etching the dielectric is usually referred to as oxide etching.
After the formation of the via hole
20
, the photoresist is stripped, and metal is deposited into the via hole
20
. The structure may be more complicated than that illustrated depending upon the special needs of different device manufacturers. The metal feature
12
may be a line rising above the dielectric layer
14
or may be a dual-damascene structure combining in the dielectric a horizontal trench and a connected vertical via. An etch stop layer may be formed between the lower and upper dielectric layer
10
,
14
to allow the etching step to stop on the etch stop layer without sputtering the underlying metal. For fluorine-based plasma etching of silica, silicon nitride is a good etch stop layer. An anti-reflection coating may be formed between the upper dielectric layer
14
and the photoresist layer
16
to aid the resolution of the photographic step used in the patterning the photomask. These additional structural features are well known in the art. Their etching is typically performed in steps separate from the dielectric etching, and an integrated etching process needs to be developed to combine the different etching steps. The invention is primarily concerned with the dielectric etching, which presents the most formidable challenges.
The thickness of the dielectric layer
14
is generally in the range of 0.7 to 1.4 &mgr;m. This thickness is not expected to decrease in advanced devices. The larger thicknesses including multiple depths of via holes are usually associated with more complex metallization structures, which offer increased device density with fewer processing steps. Via widths for chips under commercial development now may be as small as 0.18 &mgr;m. Technology for 0.13 &mgr;m widths is being developed. Widths of 0.10 &mgr;m are expected in the not too distant future.
These increasingly small widths present etching problems, particularly in view of the dielectric thickness remaining essentially constant. The via holes
20
have increasingly high aspect ratios. The aspect ratio of a via hole is the ratio between the depth of the hole to the narrowest dimension of the hole in its upper portion. At the present time, aspect ratios of 4 or 5 are found in advanced chips. In future chips, the aspect ratio will increase to 8 or 10. Such high aspect ratios present a significant challenge to oxide etching because they require a highly anisotropic etch that reaches deeply into the hole. Etching of high aspect-ratio holes also requires higher etch selectivity to photoresist due to the reduction in the oxide etch rate at greater depths in the holes. The selectivity and anisotropy required in the oxide etch has been typically accomplished using a fluorocarbon plasma chemistry which deposits a protective polymer over non-oxide materials and all vertical sidewalls. On the other hand, the combination of the fluorine plasma and underlying oxygen in the presence of energetic ion bombardment breaks down the polymer that formed at the bottom of the silica hole being etched and exposes the underlying silica to the etchant that turns it into volatile components which are pumped out from the hole, thereby etching the hole. However, if too much polymer is formed, the hole nonetheless becomes plugged with polymer and etching stops before the bottom of the hole is reached. No amount of further etching under the same conditions is effective at completing the etching process. This deleterious result is called etch stop.
The photolithography needed for such narrow features typically relies upon deep ultra-violet (DUV) light. Photoresists are available which are sensitive to DUV radiation. The thickness of the photoresist must be limited to little more than the minimum hole width. Otherwise, the photolithography becomes defocussed over the depth of the photoresist. However, photoresist is usually a carbon-based polymer that is prone to some degree of etching by most etch chemistries. As a result, the depth of the photoresist decreases from the original profile
16
′ shown in
FIG. 1
to profile
16
. Furthermore, in most etching chemistries, exposed corners are etched more quickly than planar surfaces so that the most severe selectivity problem is often manifested in facets
22
forming at the upper corners of the photoresist layer
16
around the patterned hole in the photomask. Etching of polymeric materials such as photoresist tends to produce facets that are much more curved than illustrated. A photoresist etching margin is given by the remaining height
24
on the sidewall of the photoresist
16
next to the patterned via hole
20
. If the facets
22
reach the underlying upper di

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