Chemistry: electrical and wave energy – Processes and products – Coating – forming or etching by sputtering
Reexamination Certificate
2002-09-10
2004-07-06
Versteeg, Steven (Department: 1753)
Chemistry: electrical and wave energy
Processes and products
Coating, forming or etching by sputtering
C204S298060, C204S298120, C204S298170
Reexamination Certificate
active
06758949
ABSTRACT:
BACKGROUND OF THE INVENTION
Microelectronic integrated circuit fabrication involves processes in which thin film layers are deposited and removed. Improvement in performance and speed has been attained in large part by reducing device size so that contact openings, for example, are a few microns in diameter and several microns in depth. Such improvement has also been realized with more complex structures having several layers of circuits and conductors, making the overall structure deeper, requiring contact openings and vias with higher aspect ratios. However, with the current micron-sized geometries and high aspect ratio openings (e.g., aspect ratios of 10), filling contact openings and vias with metal is accomplished using continuous plasma sputtering of a metal target. To our knowledge, other sources, such as carbon arc sources for example, are not generally employed in the processing of sub-micron semiconductor integrated circuits. One problem encountered in metal deposition in a sub-micron high aspect ratio opening is that it is difficult to thoroughly cover the bottom of the hole. This is because the sputtered metal atoms or ions tend to travel in many directions as they propagate toward the target, so that their angle of incidence is generally not parallel with the axis of the high aspect ratio opening. Therefore, many or most of the metal particles hit the side wall before they can reach the bottom of the hole and therefore form a layer on the side wall of the hole that eventually pinches off the bottom of the hole before it is completely filled.
In the recent past, this problem has been addressed by placing a relatively strong bias voltage on the workpiece (i.e., the semiconductor wafer on which the microelectronic structures are fabricated) that tends to promote metal ion trajectories that are perpendicular to the wafer surface and parallel to the axis of the high aspect ratio holes or openings. A further problem arises from the nature of the sputtered metal source, in that it tends to generate both metal ions and metal neutrals. While the ions are beneficially directed by the bias voltage on the wafer to a more perpendicular trajectory, the neutrals are not and therefore tend to deposit on the side walls of the holes, so that the problem of controlling relative rates of deposition on the side wall and bottom of a hole is not completely solved.
This latter difficulty has been addressed by increasing the proportion of metal ions in the plasma generated at the source and/or by increasing the bias voltage on the wafer. Increasing the metal ion density in the source plasma can be accomplished by magnetic confinement of the plasma near the sputtered metal target. This increase is proportional to the strength of the magnetic field used to confine the source plasma at the target, and therefore is limited by the ability to produce a strong magnetic field at the target. This approach is therefore of limited efficacy in improving metal coverage at the bottom of a high aspect ratio opening. Increasing the bias voltage on the workpiece in order to improve metal coverage at the bottom of a hole or opening is limited by the tendency to cause ion bombardment damage of the microelectronic structures on the wafer, and therefore this approach is also of limited efficacy.
The foregoing attempts to improve metal coverage at the bottom of a high aspect ratio opening are directed exclusively to solving that problem. However, even if such approaches were completely successful in solving that problem, they would still be inadequate to address current technology. This is because current microelectronic circuit technology involves sub-micron feature sizes and etched openings with aspect ratios of about ten. Current technology further involves multi-level conductor structures having long vias that must be filled by metal using fill-and-polish techniques requiring special attention not only to the coverage of the bottom surfaces of the opening but also special attention to the coverage of much deeper side walls. While an ion-rich or pure ion plasma provides best coverage of the bottom surfaces of deep narrow holes due to their generally perpendicular trajectories near the wafer surface, the neutrals tend to provide superior coverage of a side wall because of their tendency toward more oblique or non-perpendicular trajectories.
This problem occurs in processes involving copper deposition. Copper atoms deposited directly on semiconductor (silicon) surfaces or silicon dioxide layers tend to migrate out of the copper layer and into the other layer. Such migration continues over time and can ultimately lead to device failures. Therefore, copper deposition is generally preceded by deposition of a suitable barrier layer prior to deposition of copper. The barrier layer constitutes a material that tends to not migrate into the underlying layer (or any adjoining layers) and are compatible with that layer and with copper. Examples of barrier layer materials include (but are not limited to) dielectrics such as (for example) tantalum nitride, titanium nitride, etc. or conductors such as (for example) titanium or tantalum, etc. If the barrier layer is a dielectric material, then it can be advantageous to deposit a conductive seed layer (such as, for example, titanium or tantalum) over the barrier layer, and then finally depositing the copper layer.
The barrier layer and the seed layer are very thin while the copper layer fills the hole or via and therefore is relatively thick. The very thin barrier layer and seed layer present particularly difficult problems in the coverage of the side walls. Because of their thinness (relative to the copper layer that covers them), the barrier and seed layers in some cases present a lesser problem in covering high aspect ratio hole bottoms but a greater problem in covering the long and deep side walls of vias and contact openings. (Such thin layers may not present as great a risk of the pinch-off problem referred to above relating to poor metal coverage of the bottom of deep narrow holes.) In a typical example, the barrier layer is a continuous thin film of tantalum nitride that tends to be about 200 to 300 angstroms thick on horizontal surfaces and about 100 angstroms thick on vertical surfaces, and the intermediate adhesion layer is a continuous thin film of tantalum of about 100 angstroms thickness. A copper seed layer is deposited over the adhesion layer, the copper seed layer being about 1000 angstrom thick on horizontal surfaces and about 100 angstroms thick on vertical surfaces. Thereafter, a very thick copper layer is electroplated over the copper seed layer to form a fairly smooth copper surface.
Unfortunately, the problem of obtaining good side wall metal coverage has been ignored in the various techniques of the prior art. Techniques that merely enhance ion density to ensure good metal coverage at the bottom of a deep narrow hole may be unsuitable or less than optimum in current processes involving deposition of copper and underlying barrier and seed layers in high aspect ratio micron or sub-micron features. This is because the old approaches do not address the need for good side wall coverage and are directed mainly to the old problem of enhancing metal coverage at the bottom of narrow deep openings by enhancing ion density exclusively.
Therefore, what is needed is a process that is sufficiently versatile to meet the needs of current copper deposition processes involving a continuously plasma sputtered metal target and deposition of thin barrier and seed layers over long deep side walls while preserving good metal coverage of bottoms of narrow deep holes.
SUMMARY OF THE DISCLOSURE
A metal vapor deposition reactor includes a primary reactor chamber having a primary chamber enclosure comprising a ceiling and side wall. A wafer support pedestal within the primary chamber has a planar processing surface for supporting a planar semiconductor wafer. The reactor further includes a secondary reactor chamber having a secondary chamber enclosure and a metal source target
Fu Jianming
Gopalraja Praburam
Wang Wei D.
Applied Materials Inc.
Law Offices of Robert M. Wallace
Versteeg Steven
LandOfFree
Magnetically confined metal plasma sputter source with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Magnetically confined metal plasma sputter source with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Magnetically confined metal plasma sputter source with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3212678