Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-06-20
2004-03-30
Tsai, H. Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S421000, C438S003000, C438S253000
Reexamination Certificate
active
06713802
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to the fabrication of semiconductor devices, and more particularly to the fabrication of magnetic random access memory (MRAM) devices.
BACKGROUND
A more recent development in semiconductor memory devices involves spin electronics, which combines semiconductor technology and magnetics. The spin of an electron, rather than the charge, is used to indicate the presence of a “1” or “0”. One such spin electronic device is a magnetic random access memory (MRAM), which includes conductive lines positioned in a different direction, e.g., perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack or magnetic tunnel junction (MJT), which functions as a magnetic memory cell. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity into a certain direction along the wire or conductive line. A current flowing through the other conductive line induces the magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a “0” or “1”, is storable in the alignment of magnetic moments. The resistance of the magnetic memory cell depends on the moment's alignment. The stored state is read from the magnetic memory cell by detecting the component's resistive state.
An advantage of MRAMs compared to traditional semiconductor memory devices such as dynamic random access memory devices (DRAMs) is that MRAMs are non-volatile. For example, a personal computer (PC) utilizing MRAMs would not have a long “boot-up” time as with conventional PCs that utilize DRAMs. Also, an MRAM does not need to be powered up and has the capability of “remembering” the stored data. Therefore, MRAM devices are replacing flash memory, DRAM and static random access memory devices (SRAM) devices.
A magnetic stack comprises many different layers of metals and magnetic metals, and a thin layer of dielectric material having a total thickness of a few tens of nanometers. The magnetic stacks are typically built on top of copper wires embedded in an inter-level dielectric (ILD) material. The magnetic tunnel junctions (MTJ's) are positioned at intersections of underlying first conductive lines and overlying second conductive lines. MRAM devices are typically manufactured by forming a plurality of magnetic metal stacks arranged in an array, which comprise the magnetic memory cells. A memory cell array typically has conductive lines in a matrix structure having rows and columns.
One type of MRAM array uses a transistor to select each magnetic memory cell. Another type, a cross-point array, comprises an array of magnetic bits or magnetic stacks situated at the cross-points between two conductive lines. Information is stored in one of the magnetic layers of the magnetic stacks. To store the information, a magnetic field is necessary. In a cross-point array, this magnetic field is provided by a wordline and bitline current which is passed through conductive lines. Information is stored in the magnetic memory cells by aligning the magnetization of one ferromagnetic layer (information layer) either parallel or antiparallel to a second magnetic layer (reference layer). The information is detectable due to the fact that the resistance of the element in the parallel case is different from the antiparallel case. Magnetic stacks or memory cells in a cross-point array are usually selected by passing sub-threshold currents through the conductive lines, e.g., in both the x- and y-direction, and where the conductive lines cross at the cross-points, the combined magnetic field is large enough to change the magnetic orientation.
A critical challenge in MRAM technology is the patterning of the MTJ stack material. Because a MTJ stack includes a very thin junction layer, typically 10-20 Angstroms of aluminum oxide, shorting around the junction is a critical problem. In addition, interconnecting with the upper wiring level, e.g., the top magnetic layer of the magnetic stack is challenging due to the thin layers used in the MTJ stack which are easily damaged during etch processes.
SUMMARY OF THE INVENTION
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provides an improved method of patterning a MTJ stack. A material that is harder than silicon dioxide is used as a hard mask to pattern the soft layer of the MTJ stack, which increases the process window for post-MTJ stack planarization. The hard mask provides an etch stop for the trench etch stop to interconnect the MTJ to upper wiring levels. A dielectric fill material is used over the soft layer hard mask that has an increased hardness compared to that of silicon dioxide.
In accordance with a preferred embodiment of the present invention, a method of forming a bottom electrode of a magnetic memory cell includes depositing a pinning layer over a workpiece, depositing a soft layer material over the pinning layer, and depositing a first hard mask over the soft layer material, the first hard mask comprising a conductive material. The first hard mask is patterned, and the first hard mask is used to pattern the soft layer material and form at least one magnetic memory cell. A second hard mask is deposited over the first hard mask and exposed portions of the pinning layer, the second hard mask comprising a dielectric material having a Young's modulus greater than the Young's modulus of silicon dioxide. The second hard mask is patterned, and the second hard mask is used to pattern the pinning layer and form a bottom electrode.
In accordance with another preferred embodiment of the present invention, a method of manufacturing a magnetic memory device includes providing a workpiece, depositing a first insulating layer over the workpiece, and forming at least one first conductive line in the first insulating layer. A second insulating layer is deposited over the at least one first conductive line and first insulating layer, and a via is formed within the second insulating layer, wherein the via abuts the at least one first conductive line. A pinning layer is deposited over the via and second insulating layer, a soft layer material is deposited over the pinning layer, and a first hard mask is deposited over the soft layer material, the first hard mask comprising a conductive material. The first hard mask is patterned, and the first hard mask is used to pattern the soft layer material and form at least one magnetic memory cell. A second hard mask is deposited over the first hard mask and exposed portions of the pinning layer, the second hard mask comprising a dielectric material having a Young's modulus greater than the Young's modulus of silicon dioxide. The method includes patterning the second hard mask, using the second hard mask to pattern the pinning layer, and depositing a third insulating layer over the second hard mask, the third hard mask comprising a dielectric material having a Young's modulus greater than the Young's modulus of silicon dioxide. The workpiece is then planarized to remove portions of the third insulating layer from over a top surface of the first hard mask.
In accordance with yet another embodiment of the present invention, a magnetic memory device includes a workpiece, at least one first conductive line disposed over the workpiece, a pinning layer coupled to the at least one first conductive line, and a soft layer disposed over the pinning layer. The soft layer comprises a magnetic memory cell. A first hard mask is disposed over the soft layer, the first hard mask having substantially the same lateral dimensions as the soft layer, and the first hard mask being conductive. A second hard mask is disposed over the pinning layer, the top surface and sidewalls of the first hard mask, and over the sidewalls of the soft layer, wherein the second hard mask comprises substantially the same lateral dimensions as the
Infineon - Technologies AG
Slater & Matsil L.L.P.
Tsai H. Jey
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