Static information storage and retrieval – Systems using particular element – Magnetoresistive
Reexamination Certificate
2003-04-23
2004-08-17
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Systems using particular element
Magnetoresistive
C365S171000, C365S173000
Reexamination Certificate
active
06778428
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2002-0023653, filed Apr. 30, 2002, the disclosure of which is hereby incorporated herein by reference in its entirety as if set forth fully herein.
FIELD OF THE INVENTION
This invention relates to integrated circuit memory devices and operating methods thereof, and more particularly to Magnetic Random Access Memory Cells (MRAM) and operating methods thereof.
BACKGROUND OF THE INVENTION
MRAMs have been widely investigated and used as nonvolatile memory devices that can be operated at low voltage and at high speed. In an MRAM cell, data is stored in a magnetic resistor, also referred to as a Magnetic Tunnel Junction (MTJ) that includes first and second ferromagnetic layers and a tunneling insulation layer therebetween. In some embodiments, the magnetic polarization of the first ferromagnetic layer, also referred to as a free layer, is changed utilizing a magnetic field that crosses the MTJ. The magnetic field may be induced by an electric current passing around the MTJ, and the magnetic polarization of the free layer can be parallel or anti-parallel to the magnetic polarization of the second ferromagnetic layer, also referred to as a pinned layer. According to spintronics based on quantum mechanics, a tunneling current passing through the MTJ in the parallel direction may be greater than that in the anti-parallel direction. Thus, the magnetic polarizations of the free layer and the pinned layer can define the electrical resistance of the magnetic resistor, to provide an indication of the stored information in the MRAM.
It is known to provide an MRAM cell that comprises a magnetic resistor and a diode that are serially connected. See, for example, U.S. Pat. No. 5,838,608 to Zhu et al., entitled Multi-Layer Magnetic Random Access Memory and Method for Fabricating Thereof.
It is also known to provide MRAM cells that include a transistor and a magnetic resistor. See, for example U.S. Pat. No. 6,324,093 to Perner et al. entitled Write-Once Thin-Film Memory; U.S. Pat. No. 6,349,054 to Hidaka entitled Thin Film Magnetic Memory Device Including Memory Cells Having a Magnetic Tunnel Junction; U.S. Pat. No. 6,359,805 to Hidaka entitled Thin Film Magnetic Memory Device Capable of Easily Controlling a Data Write Current; U.S. Pat. No. 6,418,046 to Naji entitled MRAM Architecture and System; and U.S. Pat. No. 6,490,217 to Debrosse et al. entitled Select Line Architecture for Magnetic Random Access Memories.
In many MRAM cells, the magnetic resistor is a planar magnetic resistor, which includes planar ferromagnetic layers and a planar insulating layer therebetween. See, for example, the above-cited patents to Perner et al. and Hidaka. It may be difficult to shrink a planar magnetic resistor to provide higher integration density due to the reduced spins at the edges of the ferromagnetic layers due to defects therein. This phenomena is often called the “edge effect” or the “shape effect”.
It is also known to use nonplanar magnetic resistors in MRAMs. See, for example, U.S. Pat. No. 6,436,526 to Odagawa et al. entitled Magneto-Resistance Effect Element, Magneto-Resistance Effect Memory Cell, MRAM and Method for Performing Information Write to or Read From the Magneto-Resistance Effect Memory Cell at Column 18, lines 34-36, and U.S. Pat. No. 6,266,289 to Dubovik et al. entitled Method of Toroid Write and Read, Memory Cell and Memory Device for Realizing the Same.
SUMMARY OF THE INVENTION
Some embodiments of the present invention provide MRAM cells that comprise a magnetic resistor including first and second terminals, an access transistor that is connected to the first terminal, and a bit line that also is connected to the first terminal. A reading word line is connected to the second terminal, and a word line is connected to the access transistor. In other embodiments, the access transistor includes a controlling electrode, such as a field effect transistor (FET) gate, and first and second controlled electrodes, such as an FET source and drain, wherein the word line is connected to the controlling electrode (gate), and the first terminal and the bit line are connected to the second controlled electrode (drain). In other embodiments, the bit line extends along a first direction and the word line and the reading word line extend along a second direction that is different from the first direction. In still other embodiments, the first terminal comprises a conductive axis, the magnetic resistor at least partially surrounds the conductive axis to define an outer surface of the magnetic resistor, and the second terminal comprises at least a portion of the outer surface.
MRAM cells according to other embodiments of the invention include an integrated circuit substrate, an access transistor in the integrated circuit substrate, at a face thereof, and a conductive axis on the integrated circuit substrate, including a first end that is adjacent and connected to the access transistor, and a second end that is remote from the access transistor. A magnetic resistor at least partially surrounds the conductive axis between the first and second ends thereof. A bit line is connected to the second end of the conductive axis and extends along a direction that is parallel to the face. A reading word line is connected to the magnetic resistor and also extends along the direction that is parallel to the face. In other embodiments, a word line is connected to the access transistor and also extends along a direction that is parallel to the face. In still other embodiments, the bit line extends along a first direction that is parallel to the face and the reading word line extends along a second direction that is also parallel to the face but is different from the first direction.
In still other embodiments, the magnetic resistor includes a first ferromagnetic layer that at least partially surrounds the conductive axis, a tunneling insulation layer that at least partially surrounds the first ferromagnetic layer and a second ferromagnetic layer that at least partially surrounds the tunneling insulation layer. The first ferromagnetic layer is connected to the conductive axis and the second ferromagnetic layer is connected to the reading word line. In some embodiments, the first ferromagnetic layer, the tunneling insulating layer and the second ferromagnetic layer are coaxial and may be polygonal or nonpolygonal in cross-section. Each of these elements also may be of uniform or non-uniform cross-sectional size along the conductive axis. A reading word line electrode also may be provided in some embodiments, that at least partially surrounds the second ferromagnetic layer and that is connected to the second ferromagnetic layer.
Still other embodiments of the present invention provide methods of operating an MRAM cell that includes a magnetic resistor including first and second terminals, an access transistor that is connected to the first terminal, a bit line that also is connected to the first terminal and a reading word line that is connected to the second terminal. In these embodiments, the MRAM cell is written by turning on the access transistor to force writing current into the first terminal and thereby change the resistance of the magnetic resistor. Reading is performed by applying voltage between the bit line and the reading word line, and sensing current through the magnetic resistor in response thereto. In other embodiments, writing is performed by activating the word line to turn on the access transistor. In still other embodiments, writing is performed by turning on the access transistor to force writing current into the conductive axis, and thereby change the resistance of the magnetic resistor.
REFERENCES:
patent: 5838608 (1998-11-01), Zhu et al.
patent: 6266289 (2001-07-01), Dubovik et al.
patent: 6324093 (2001-11-01), Perner et al.
patent: 6349054 (2002-02-01), Hidaka
patent: 6359805 (2002-03-01), Hidaka
patent: 6418046 (2002-07-01), Naji
patent: 6436526 (2002-08-01), Odagawa et al.
patent: 6490217 (2002-12-01), DeBross
Hoang Huan
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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