Magnetic memory device implementing read operation tolerant...

Details Magnetic memory device implementing read operation tolerant... Magnetic memory device implementing read operation tolerant...

2005-02-08

2005-02-08

Auduong, Gene N. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S158000, C365S189060

Reexamination Certificate

active

06853599

ABSTRACT:
A magnetic memory device includes a memory cell array block and a reference memory cell array block having a plurality of magnetic memory cells arranged, respectively, at intersections of wordlines, digit lines, and bitlines, and reference wordlines, the digit lines, and a reference bitline, a first bitline clamp circuit coupled to a bitline to which a first selected magnetic memory cell is connected and supplying a first current to the first selected magnetic memory cell through the bitline, second and third bitline clamp circuits coupled to respective upper and lower ends of the reference bitline, for supplying a second current to selected magnetic memory cells in the reference memory cell array block through the reference bitline, and a sense amplifier for sensing and amplifying currents on first and second data lines, respectively connected to the bitline and the reference bitline, to judge data of the first selected magnetic memory cell.

REFERENCES:
patent: 6445612 (2002-09-01), Naji
patent: 6574129 (2003-06-01), Tran
patent: 6700814 (2004-03-01), Nahas et al.
patent: 20030123281 (2003-07-01), Iwata et al.
patent: 20040022097 (2004-02-01), Cho
2002 Symposium on VLSI Circuits Digest of Technical Papers, Durlam et al.—A low power 1Mbit MRAM, etc.. pp. 158-161.

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