‘Via first’ dual damascene process for copper...

Details ‘Via first’ dual damascene process for copper... ‘Via first’ dual damascene process for copper...

2000-06-30

2003-06-10

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S634000, C438S636000, C438S637000, C438S638000, C438S672000, C438S675000

Reexamination Certificate

active

06576550

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit devices using copper for interconnecting discrete circuit components as part of the back-end-of-the-line processing of semiconductive silicon wafers, and particularly, to modifications in wafer processing needed to protect the copper during chemical etching when the via is etched before the trench in a dual Damascene process.
BACKGROUND OF THE INVENTION
The demand for faster integrated circuits is driving the technologists to make the solid state components on a chip smaller and to increase the packing density. As a result of this demand, the interconnect metallurgy is shifting from aluminum-based metals to copper, which has a lower resistivity. The higher conductivity and lower cost of copper makes it very desirable for interconnecting the circuit components. Also, copper has a better resistance to electromigration failures than Al or Al—Cu and therefore, better reliability.
Although copper has very favorable electrical properties, it is prone to oxidation and corrosion when it comes in contact with some commonly-used processing chemicals. Therefore, it is critical that the processes used in conjunction with copper metallization be free from these environments when the copper is exposed, that is, not covered, during processing. Al and Al—Cu back-end-of-the-line metallizations are not prone to corrosion because of the protective oxide covering the metal surfaces in these materials.
Copper is a very viable material as the back-end-of-the-line metal when the single or dual Damascene processes are used. The Damascene process makes use of a series of trenches formed in an insulating layer. After the trenches are overfilled with copper, a chemical mechanical polishing process (CMP) is used to remove the overfill. Trenches are to be distinguished from vias. Trenches are extended grooves, typically extending parallel to the top surface of the silicon chip, that are patterned to interconnect circuits on the same level of the back-end-of-the-line process whereas vias are holes, typically extending normal to the surface, that are patterned to connect the metal lines from layer to layer.
Present technology uses a ‘trench first’ approach. Initially, the ‘via first’ approach was compromised because of the need for multiple layers of a relatively thick silicon nitride film. The silicon nitride, which protected the copper during processing had to, by necessity, remain behind in many of the active areas. These silicon nitride layers, however, resulted in a substantial increase in the dielectric properties of the stack and degraded the performance of the circuit. If the silicon nitride films were made thinner, they would degrade during the via etch. Also, the via etch could etch into the oxide that defines the trench. Even small changes in the line definition can cause serious reliability problems when 0.25 um ground rules are in place.
Since copper is known to be very sensitive to its environment, photoresists, which typically contain sulfur, and oxidizing chemicals should not be permitted to come in contact with the copper surfaces during processing. In this invention silicon nitride is used both as a protective layer for the copper and as an etch stop.
The ‘trench first’ approach however, also has its limitations. These limitations are associated with the photolithographic processing of the wafer. The difficulties occur when the trench configurations lead to differences in photoresist thicknesses. The thickness variations are seen in either broad trenches (wide lines) or very dense trenches (closely spaced narrow lines) as required, for example, by DRAMS and cause printing distortions of the via images.
The present invention seeks to provide a protective layer of silicon nitride over the copper while using a novel approach for assuring that the silicon nitride is not damaged during the simultaneous etching of the vias and trenches.
SUMMARY OF THE INVENTION
This invention relates to the use of the preferred ‘via first’ approach for forming vias (openings, holes) and trenches (grooves) in a passivating layer by using the double Damascene process.
In an exemplary embodiment, a contact metallurgy is deposited into a patterned glass layer (e.g., boron phospho silicate glass (BPSG)] and the glass is planarized. A different insulating material, such as silicon oxide, is then deposited onto the glass layer and patterned to form shallow via openings aligned with the contacts. The vias are filled with copper and the surface is planarized with a chem-mech polish. A thin silicon nitride layer is deposited onto the planarized insulator surface to act as a barrier layer/etch stop.
An SiO
2
layer is deposited over the silicon nitride layer and patterned by a conventional photolithographic technique to form therein via holes aligned with the earlier vias.
In the present invention an unconventional use is advantageously made of an anti-reflective coating material (ARC) which is spun onto the wafer. The coating of ARC fills the vias and covers the rest of the surface with a thin ARC layer. With the ARC material in place, photoresist is spun onto the wafer and patterned to form the trench configuration. The SiO
2
layer, which contains the vias, is etched again to form the trenches. During the trench etching the ARC material is also etched but at a rate different from the SiO
2
. As a result of this differential etch rate, a plug of ARC material remains in the bottom of the vias after the trench open process has been completed. This ARC plug protects the silicon nitride from degrading which, in turn, protects the underlying copper because the etchant never comes into contact with the copper.
To this end, one feature of the invention is the use of a silicon nitride film to protect the copper during the etching of the insulating layers. In particular this silicon nitride layer should be thin so that the increase in the dielectric properties of the stack is kept to a minimum.
Another feature of the invention is on the use of an anti-reflective coating (ARC) to protect the silicon nitride layer. Normally, in the fabrication of semiconductive chips, photoresist materials are used as protective layers in addition to providing a photolithographic medium for component definition of the silicon, insulators and metals.
A related feature of the invention involves the etching of the ARC layer so as to insure that it is not entirely removed from the vias. After the etching of the vias and trenches has been completed, the ARC coating is removed as part of the photoresist strip process.
Viewed from a first process aspect, the present invention is directed to a method for forming over a semiconductive wafer, which contains therein and/or thereon devices having conductive contact regions, an interconnection pattern that uses copper in at least some vias and some trenches through insulating layers overlying a top surface of the semiconductor wafer. The method comprises the steps of: forming a first insulating layer over the device; forming vias from a top surface of the first insulating layer therethrough with the vias being in communication with the contact regions of the device; filling the vias with a conductor; forming a second insulating layer over the first insulating layer; forming vias through the second insulating layer which are in communication with the conductor filled vias in the first insulating layer; filling the vias through the second insulating layer with copper; forming a third insulating layer over a top surface of the second insulating layer; forming a fourth insulating layer over a top surface of the third insulating layer, the fourth insulating layer having a different etch characteristic than the third insulating layer; patterning and etching the fourth insulating layer to form vias therethrough which are separated from the copper-filled vias through the second insulating layer by the third insulating layer but are aligned with the vias through the second insulating layer; forming an anti-reflective layer over a top surface of th

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