Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-01-18
2003-04-08
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06546525
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an LSI testing apparatus and, more particularly, to an LSI testing apparatus and testing method adapted to reduce power dissipation.
2. Description of the Background Art
Conventional LSI testing apparatuses are provided with test programs corresponding to specific LSIs and are controlled thereby in carrying out tests on such LSIs.
FIG. 9
is a flowchart of steps in which a conventional LSI testing apparatus typically operates.
Immediately after power-up, the conventional LSI testing apparatus becomes capable of executing all its functions using all its pins. Illustratively, as shown in
FIG. 9
, a test program is compiled and loaded in step S
1
. After test data are set to the hardware in step S
2
, tests are carried out in step S
3
.
In that flow of steps, when some pins or functions of the LSI testing apparatus are deemed unnecessary for the LSI test in question, those portions of apparatus hardware which are not relevant to the LSI test are nevertheless left activated.
Structured as outlined above, conventional LSI testing apparatuses have had part of their hardware dissipating more power than is actually needed. This has led to elevated running costs of the LSI testing apparatuses regardless of the LSIs to be tested. Where varieties of LSIs are to be tested at a semiconductor factory, the extra running costs tend to make LSI test costs unreasonably high.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above circumstances and provides an LSI testing apparatus whereby any pins and functions not used in testing a specific LSI are detected so as to save power in terms of such unused pins and functions and whereby any currently inactive pins and functions to be activated for testing a different LSI are also detected so that aging of newly tested LSI will be completed in a short time.
The above objects of the present invention are achieved by an LSI testing apparatus described below. The apparatus includes a plurality of pins as well as function units which supply the pins with LSI testing signals, which have functions for making judgments on tests, and which are furnished for each of the pins. Any unused pin and function are detected so as to stop the function unit corresponding to the detected pin and function. According to the apparatus, power dissipation is reduced in terms of unused pins and functions.
The above objects of the present invention are achieved by an LSI testing apparatus described below. The apparatus includes a plurality of pins as well as function units which supply the pins with LSI testing signals, which have functions for making judgments on tests, and which are furnished for each of the pins. Upon testing, any pin and function having made an unused to used state transition are detected so as to warm up the function units corresponding to the detected pin and function.
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Funakura Teruhiko
Nakase Yasuhide
Sugimoto Masaru
Lin Sun James
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Siek Vuthe
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