LSI, test pattern generating method for scan path test, LSI...

Details LSI, test pattern generating method for scan path test, LSI... LSI, test pattern generating method for scan path test, LSI...

2007-08-28

2007-08-28

Tu, Christine T. (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

11293166

ABSTRACT:
Registers119and120for power control or power-off signals in an LSI are set as a dedicated chain and a control signal can be controlled desirably from the outside so that the states of the registers119and120can be monitored easily. In a test pattern generating method for a scan path test, the relation between values of the registers for the power control or power-off and power supplies to be controlled is set as an option in order to control the registers119and120for the power control or power-off. In this manner, a pattern in which the power control function or the power-off function of the LSI is taken into consideration can be produced.

REFERENCES:
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patent: 6972598 (2005-12-01), Yoo
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patent: 09-311157 (1997-12-01), None
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Abramovici et al.;Digital Systems Testing and Testable Design; pp. 364-366 and pp. 488-489.

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