Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-11-20
2004-01-06
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S701000, C710S007000
Reexamination Certificate
active
06675332
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a LSI device used for communication, and particularly to a LSI device used for communication based on a high speed serial bus.
2. Description of the Related Art
A kind of LSI device used for communication is well known which is defined in the “IEEE Standard for a High Performance Serial Bus, IEEE Standard, 1394” issued in 1995 by IEEE (Institute of Electrical and Electronic Engineers), and have been widely used.
The communication LSI device according to the IEEE Standard, 1394 has a control circuit called a physical layer circuit and is structured so as to receive control command signals through a link circuit corresponding to an external upper layer. In practical use of this communication LSI device in a host unit including a high speed serial bus, a plurality of LSI devices are used in correspondence with a plurality of serial buses which are usually included in the host unit. Therefore, the physical layer control circuit has a function to construct a tree connection (tree identifications (Ids) in the tree structure) of the plurality of LSI devices and to carry out configuration including allocation of identification numbers (self IDs) to individual LSI devices in the tree structure.
In general, in a product test process of semiconductor integrated circuits (LSI devices), a reliability test is carried out by use of a bias temperature screening method in which products are operated for a long time at a high temperature so that heat and electric stresses are applied to the products. Thus, initial failures are detected, so that the products having the initial failures are removed to obtain high reliability.
The bias temperature screening method is classified into a static bias temperature screening method and a dynamic bias temperature screening method. In the static bias temperature screening method, a non-operating LSI device is left under a high temperature condition in which only a power source voltage is supplied to the LSI devices. In this case, the circuit does not operate so that a part of the circuit does not receive electric stress. On the other hand, in the dynamic bias temperature screening method, a LSI device to be tested is left under a high temperature condition, and a signal pattern is externally supplied to the LSI device to operate the LSI device steadily. Thus, the test can be carried out in the state that heat and electric stresses are imposed to the LSI device. Therefore, the dynamic bias temperature screening method is much more effective among the bias temperature screening methods.
However, the test environment in which the dynamic bias temperature screening method is carried out needs to be constructed in a closed and limited space such as a constant temperature vessel. Hence, a device such as a pattern generator, which supplies a test pattern for the LSI device to be test, is difficult to be located in the test environment.
FIG. 1
is a block diagram showing the structure of a physical layer circuit
100
of a conventional communication LSI device. Referring to
FIG. 1
, the physical layer circuit
100
of the conventional communication LSI device is composed of a state machine
1
, a timer
2
, a link interface (I/F) circuit
3
and an inverter
4
. The state machine
1
controls the entire operation of the communication LSI device. The timer
2
is used in the control of a state transit time of the state machine
1
. The inverter
4
inverts a low active reset signal RB inputted from a reset terminal TR to output as a high active rest signal R.
The link interface circuit
3
functions as an interface to an external link circuit. The link interface circuit
3
inputs a command signal Q from the external link circuit through a command signal terminal TQ. The interface circuit
3
interprets the command signal Q and outputs an instruction IS to the state machine
1
.
The state machine
1
receives a high active reset signal R and starts a predetermined configuration operation. Upon completion of the configuration operation, the state machine
1
outputs a high active flag signal F (called subaction gap) to the link interface circuit
3
. An output from the timer
2
is supplied to the state machine
1
, and the time of the configuration operation such as the time for the flag signal F to be outputted is controlled.
Next, operation of the physical layer circuit
100
of the conventional communication LSI device will be described with reference to FIG.
1
and
FIGS. 2A
to
2
F.
FIGS. 2A
to
2
F are timing charts showing waveforms at respective sections of the conventional physical layer circuit. At first, when the reset signal RB of a low level shown in
FIG. 2A
is inputted from the reset terminal TR, the reset signal R as the output of the inverter
4
is changed to a high level, as shown in FIG.
2
D. At this time, the state machine
1
is reset to enter into an “idle” state. Thereafter, the reset signal R is changed to the low level when the reset terminal changes to the high level, and the reset state of the state machine
1
is released. Upon the release of the reset state, the state machine
1
starts a configuration operation as follows.
That is, in the configuration operation, under time control by the timer
2
, the state S of the state machine
1
changes to a “bus reset” state, a “tree ID” state, a “self ID” state and the “idle” state, as shown in FIG.
2
B. In the “bus reset” state, a serial bus as a connection target is initialized. In the “tree ID” state, a tree structure is constructed to include another communication LSI device in a device associated with the target serial bus. In the “self ID” state, identification numbers are allocated to the respective communication LSI devices in the tree structure. Then, the state S of the state machine
1
returns to the “idle” state. When the timer
2
counts a predetermined time after the return of the state machine
1
to the “idle” state, the state machine
1
then outputs a pulse of the high level as the flag signal F to end the configuration operation, as shown in FIG.
2
C.
The link interface circuit
3
is not inputted with a command signal Q from an external link circuit to the end of the configuration operation. As a result, the command signal terminal TQ is in the low level and the instruction IS indicates “no request”, as shown in FIG.
2
F.
After completion of the configuration operation, the state S of the state machine
1
keeps staying in the “idle” state, waiting for a command signal to be inputted through the command signal terminal TQ from the external link circuit. Upon input of a transmission command signal from the command signal terminal TQ, the link interface circuit
3
outputs a “transmission request” instruction as an instruction IS to the state machine
1
, as shown in FIG.
2
F. Upon receipt of the “transmission request” instruction, the state machine
1
is changed to a “transmission” state to execute transmission operation, as shown in
FIG. 2
b
. Then, the state machine
1
returns to the “idle” state. When the timer
2
counts a predetermined time after the return of the state machine
1
to the “idle” state, the state machine
1
outputs a pulse of the high level as the flag signal F, as shown in FIG.
2
C.
As described above, the conventional communication LSI device does not operate after the end of the configuration operation unless a pattern signal (command signal) is inputted to the internal circuit of the LSI device is through the external command signal terminal TQ.
Also, in the closed test environment necessary for carrying out the dynamic bias temperature screening, even if the communication LSI device to be tested can be stored in a constant temperature vessel after the configuration operation, it is impossible to connect a pattern generator with the external terminal TQ of the LSI device to be tested to supply a test pattern. Therefore, a predetermined test cannot be carried out.
In conjunction with the above description, a single chip microcomputer is disclosed i
Chiba Katsuharu
Suzuki Koichiro
Baker Stephen M.
Chaudry Mujtaba
NEC Corporation
Sughrue & Mion, PLLC
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