LPCVD gate hard mask

Details LPCVD gate hard mask LPCVD gate hard mask

2006-07-25

2009-06-16

Lebentritt, Michael S (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S584000, C438S706000, C438S711000, C438S723000, C438S724000, C257SE21197, C257SE21206, C257SE21208, C257SE21257, C257SE21267

Reexamination Certificate

active

07547621

ABSTRACT:
A gate hard mask is deposited on a gate structure using low pressure chemical vapor deposition (LPCVD). By doing so, the wet etch removal ratio (WERR) of the gate hard mask relative to the underlying polysilicon gate layer is increased when compared to prior art hard masks. The LPCVD gate hard mask will not only etch faster than prior art hard masks, but it will also reduce undercutting of the gate oxide. To provide additional control of the wet etch rate, the LPCVD hard mask can be annealed. The annealing can be tailored to achieve the desired etching rate.

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