Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-11-08
2003-07-29
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000
Reexamination Certificate
active
06599802
ABSTRACT:
BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to integrated circuit structures and fabrication methods, and particularly to CMOS integrated circuits which include both normal logic transistors and lower-threshold transistors with leakage characteristics which would not be acceptable for all transistors on chip.
BACKGROUND
As power supply voltages are scaled lower, one of the difficult tradeoffs for process and circuit designers has been where to set threshold voltages. Reducing the magnitude of threshold voltages produces faster switching, but higher leakage currents.
One known approach to this dilemma is to provide BOTH standard and reduced-threshold-voltage transistors: the reduced-threshold-voltage transistors can be used for fast signal propagation, and the standard transistors can be used, for example, to power off signal paths or blocks which are not being used.
This approach is very attractive, but previous implementations have significantly increased process complexity. For example, in a CMOS process four types of small MOS transistors would have to be specified, in addition to any bipolar, high-voltage, or other special device types.
Low Vt Transistor by Tailoring Effective Channel Length
The present application discloses a way to fabricate low Vt transistors that decreases the number of process steps. In the preferred embodiment, a single mask is used to completely or partially remove the oxide spacer surrounding the polysilicon gate on the low Vt transistors only. This is followed by the standard CMOS process, except that no special implants are necessary to alter the threshold voltages of the low Vt transistors. This is because the effective channel length of the low Vt transistors is smaller than that for the core transistors for the same extension implants.
Advantages of the disclosed methods and structures, in various embodiments, can include one or more of the following:
reduced number of mask steps needed for fabricating different threshold voltage transistors in same process;
reduced number of implant steps for low Vt transistors.
REFERENCES:
patent: 5998274 (1999-12-01), Akram et al.
patent: 6111298 (2000-08-01), Gardner et al.
patent: 6432778 (2002-08-01), Lai et al.
Brady III W. James
Garner Jacqueline J.
Lee Calvin
Smith Matthew
Telecky , Jr. Frederick J.
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